MAX5825PMB1# Maxim Integrated, MAX5825PMB1# Datasheet
MAX5825PMB1#
Specifications of MAX5825PMB1#
Related parts for MAX5825PMB1#
MAX5825PMB1# Summary of contents
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Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I General Description The MAX5823/MAX5824/MAX5825 8-channel, low-power, 8-/10-/12-bit, voltage-output digital-to-analog converters (DACs) include output buffers and an internal 3ppm/°C reference that is selectable to be 2.048V, 2.500V, or 4.096V. ...
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... Differential Nonlinearity (Note 5) Offset Error (Note 6) Offset Error Drift Gain Error (Note 6) Gain Temperature Coefficient Zero-Scale Error Full-Scale Error Maxim Integrated MAX5823/MAX5824/MAX5825 Maximum Continuous Current into Any Pin .................... Q50mA Operating Temperature .................................... -40NC to +125NC + 0.3V) and +6V DD Storage Temperature ....................................... -65NC to +150NC Lead Temperature (TSSOP only)(soldering, 10s) ...........+300NC Soldering Temperature (reflow) ...
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... Resistive Load Handling Short-Circuit Output Current DC Power-Supply Rejection DYNAMIC PERFORMANCE Voltage-Output Slew Rate Voltage-Output Settling Time DAC Glitch Impulse Channel-to-Channel Feedthrough (Note 8) Digital Feedthrough Power-Up Time Maxim Integrated MAX5823/MAX5824/MAX5825 = 0V 200pF, R GND L L SYMBOL CONDITIONS No load 2kI load to GND 2kI load to V ...
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... DDIO (Note 3) PARAMETER Output Voltage-Noise Density (DAC Output at Midscale) Integrated Output Noise (DAC Output at Midscale) Output Voltage-Noise Density (DAC Output at Full Scale) Integrated Output Noise (DAC Output at Full Scale) Maxim Integrated MAX5823/MAX5824/MAX5825 = 0V 200pF, R GND L L SYMBOL CONDITIONS f = 1kHz External reference ...
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... Reference Line Regulation POWER REQUIREMENTS Supply Voltage I/O Supply Voltage Supply Current (Note 11) Power-Down Mode Supply Current Digital Supply Current DIGITAL INPUT CHARACTERISTICS (SCL, SDA, ADDR0, ADDR1, LDAC, CLR, M/Z) Input High Voltage (Note 11) Maxim Integrated MAX5823/MAX5824/MAX5825 = 0V 200pF, R GND L L SYMBOL CONDITIONS V ...
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... Hold Time Repeated for a START Condition SCL Pulse Width Low SCL Pulse Width High Setup Time for Repeated START Condition Data Hold Time Data Setup Time SDA and SCL Receiving Rise Time Maxim Integrated MAX5823/MAX5824/MAX5825 = 0V 200pF, R GND L L SYMBOL CONDITIONS 2.2V < V ...
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... Note 12: Unconnected conditions on the ADDR_ inputs are sensed through a resistive pullup and pulldown operation; for proper operation, ADDR_ inputs must be connected to V SDA t LOW t F SCL t HD;STA t CLPW S CLR t CLRSTA LDAC Figure Serial Interface Timing Diagram Maxim Integrated MAX5823/MAX5824/MAX5825 = 0V 200pF, R GND L L SYMBOL CONDITIONS SU;STO 2. ...
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... CODE (LSB) OFFSET AND ZERO-SCALE ERROR vs. SUPPLY VOLTAGE 1 2.5V (EXTERNAL) REF 0.8 NO LOAD 0.6 ZERO-SCALE ERROR 0.4 0.2 0 -0.2 OFFSET ERROR -0.4 -0.6 -0.8 -1.0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 SUPPLY VOLTAGE (V) Maxim Integrated MAX5823/MAX5824/MAX5825 Typical Operating Characteristics INL vs. CODE 1 REF 0.8 NO LOAD 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 4096 0 512 1024 1536 2048 2560 CODE (LSB) INL AND DNL vs. SUPPLY VOLTAGE 1 ...
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... SUPPLY VOLTAGE (V) SETTLING TO ±1 LSB ( 5V 2kI REF L V OUT 0.5V/div 1/4 SCALE TO 3/4 SCALE 3.75µs TRIGGER PULSE 5V/div 4µs/div Maxim Integrated MAX5823/MAX5824/MAX5825 Typical Operating Characteristics (continued) SUPPLY CURRENT vs. TEMPERATURE 2 DDIO V = FULL SCALE 4.096V, V OUT_ ALL DACS ENABLED 1.8 NO LOAD ...
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... EDGE 0V 10µs/div CHANNEL-TO-CHANNEL FEEDTHROUGH ( 5V REF TRANSITIONING DAC FULL SCALE STATIC DAC: MIDSCALE ANALOG CROSSTALK = 3.3nV*s 4µs/div Maxim Integrated MAX5823/MAX5824/MAX5825 Typical Operating Characteristics (continued) = 2kI 200pF MAX5823 toc18 TRIGGER PULSE MAX5823 toc20 V SCL 5V/div ...
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... DD 100 0 -100 -200 -300 -400 -500 -30 -20 - (mA) OUT Maxim Integrated MAX5823/MAX5824/MAX5825 Typical Operating Characteristics (continued +25NC 200pF) L MAX5823 toc24 0.585 LSB/div NO LOAD LOADED 4µs/div = 5V 10kI) L MAX5823 toc26 20ns/div HEADROOM AT RAILS vs. OUTPUT CURRENT (V 5.00 4 ...
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... MIDSCALE UNLOADED 4s/div V DRIFT vs. TEMPERATURE REF 2.8 2.9 3.0 3.2 3.3 3.4 3.6 3.7 3.9 4.0 4.1 TEMPERATURE DRIFT (ppm/°C) Maxim Integrated MAX5823/MAX5824/MAX5825 Typical Operating Characteristics (continued) = 4.5V) REF MAX5823 toc31 V = 12µV P-P 2µV/div = 2.5V) REF MAX5823 toc33 V = 15µV P-P 2µV/div REFERENCE LOAD REGULATION INTERNAL REFERENCE -0 ...
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... Output DACs with Internal Reference and I (MAX5825, 12-bit performance +25°C, unless otherwise noted.) A WATCHDOG TIMER PERIOD HISTOGRAM FREQUENCY (Hz) Maxim Integrated MAX5823/MAX5824/MAX5825 Typical Operating Characteristics (continued) 1005 1000 995 990 985 980 975 2.7 WATCHDOG TIMER FREQUENCY vs. TEMPERATURE 1010 ...
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... V DDIO 12 A4 ADDR1 13 A5 ADDR0 14 B5 SCL 15 B4 SDA 16 C5 IRQ 17 C4 CLR 18 D5 LDAC 19 D4 GND 20 C3 M/Z Maxim Integrated MAX5823/MAX5824/MAX5825 TOP VIEW 20 M GND A 18 LDAC 17 CLR B 16 IRQ 15 SDA C 14 SCL 13 ADDR0 D 12 ADDR1 11 V DDIO Reference Voltage Input/Output ...
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... V OUT REF where D = code loaded into the DAC register, V reference voltage resolution. Maxim Integrated MAX5823/MAX5824/MAX5825 The user interface is separated from the DAC logic to minimize digital feedthrough. Within the serial interface is an input shift register, the contents of which can be routed to control registers, individual, or multiple DACs as determined by the user command ...
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... A software CONFIG CLRSTA command can be used to configure the clear operation of each DAC independently. The MAX5823/MAX5824/MAX5825 feature an interface watchdog timer with programmable timeout duration. This monitors the I/O interface for activity and integrity. If the Maxim Integrated MAX5823/MAX5824/MAX5825 External Reference . DD for a M/Z Input ) ...
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... V of 5.5V; bus voltages lower than V mended and may result in significantly increased inter- face currents. The MAX5823/MAX5824/MAX5825 digital inputs are double buffered. Depending on the command SMBus is a trademark of Intel Corp. Maxim Integrated MAX5823/MAX5824/MAX5825 ) Table 1. I DDIO I C Serial Interface ...
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... SCL A ACK. GENERATED BY MAX5823/MAX5824/MAX5825 Figure Single Register Write Sequence Maxim Integrated MAX5823/MAX5824/MAX5825 I C Slave Address MAX5825 devices acknowledge and respond to the 2 broadcast device address 00101000, regardless of the state of the address pins. The broadcast mode is intend- ed for use in write mode only (as indicated by R the address given) ...
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... N SCL A ACK. GENERATED BY MAX5823/MAX5824/ MAX5825 Figure 6. Standard Register Read Sequence Maxim Integrated MAX5823/MAX5824/MAX5825 C Write Operations Combined Format I Each readback sequence is framed by a START or Repeated START condition and a STOP condition. Each word is 8 bits long and is followed by an acknowledge clock pulse as shown in the address of the MAX5823/MAX5824/MAX5825 with R indicate a write ...
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... All Other Commands (MAX5825) All Other Commands (MAX5824) All Other Commands (MAX5823) Maxim Integrated MAX5823/MAX5824/MAX5825 11000001 and 11000010, respectively) behave identi- cally to the LOAD command with all DACs selected. Modified readback of the POWER register is supported for the POWER command (B[23:20] = 0100). The power ...
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... C SLAVE ADDRESS START SDA SCL WRITE ADDRESS BYTE # SLAVE ADDRESS ACK. GENERATED BY MAX5823/MAX5824/MAX5825 A Figure 7. Interface Verification Register Read Sequences Maxim Integrated MAX5823/MAX5824/MAX5825 B12 B11 B10 ...
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... SCL line but the MAX5823/MAX5824/MAX5825 take over the SDA line. The final three bytes in the frame contain the command and register data written in the first transfer Maxim Integrated MAX5823/MAX5824/MAX5825 presented for readback, followed by a STOP condition. If additional bytes beyond those required to readback the requested data are provided, the MAX5823/MAX5824/ MAX5825 will continue to readback ones ...
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... Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I WD_MASK Maxim Integrated MAX5823/MAX5824/MAX5825 2 C Interface CLEAR_ENB LDAC_ENB GATE_ENB 0 DAC 0 DAC 1 DAC 1 DAC 2 DAC 2 DAC 3 DAC 3 DAC 4 DAC 4 DAC 5 DAC 5 DAC 6 DAC 6 DAC 7 DAC 7 DAC 23 ...
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... Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I 0 DAC 1 DAC 2 DAC 3 DAC 4 DAC 5 DAC 6 DAC 7 DAC Maxim Integrated MAX5823/MAX5824/MAX5825 2 C Interface 24 ...
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... DAC(s) as well as the DAC register content of all DACs. Channels for which CODE content has not been modified since the last LOAD or LDAC operation will not be updat reduce digital crosstalk. Issuing this command with Maxim Integrated MAX5823/MAX5824/MAX5825 RETURNn Command Table 5. DAC Selection ...
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... Watchdog HOLD or CLR configurations as set by the CONFIG command. See the CONFIG register definition for details. Maxim Integrated MAX5823/MAX5824/MAX5825 WDOG Command any register. LDAC and CLR inputs still function after a watchdog timeout event. Medium (01): A WD_REFRESH command must be execut order to refresh the watchdog timer ...
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... RF2 REF Command Default Value → 0 Command Byte Maxim Integrated MAX5823/MAX5824/MAX5825 REF Command tinue to function normally and are not reset (unless reset by a watchdog timeout). The WD_REFRESH command (B[23:0] = 0011_0010_ 1001_0110_0011_0000) will refresh the watchdog timer. This is the only command which will refresh the watch- dog timer if the device is configured with a safety level of medium, high, or max ...
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... DISABLE (WC = 00): Watchdog timeout does not affect the operation of the selected DAC. GATE (WC = 01): DAC code is gated to DEFAULT value in response to watchdog timeouts. Unless otherwise prohibited by the watchdog safety level, LDAC, CLR, Maxim Integrated MAX5823/MAX5824/MAX5825 POWER Command occurred and the watchdog timer is configured with a safety level of high or max. ...
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... CONFIG Command Reserved Default Value → Command Byte Maxim Integrated MAX5823/MAX5824/MAX5825 LDB = 1: DAC latch is transparent, the CODE register content controls the DAC output directly. Clear Configuration: CLEAR_ENB setting is written by CLB (B3); CLEAR_ENB operation is as follows: CLB = 0: Clear input and command functions impact the DAC (default), clearing CODE and DAC registers to their DEFAULT value ...
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... DEFAULT Command Reserved Default Value → Command Byte Maxim Integrated MAX5823/MAX5824/MAX5825 DEFAULT Command Available default values (DF[2:0]): M/Z (000): DAC channel defaults to value as selected by the M/Z input (default). ZERO (001): DAC channel defaults to zero scale. MID (010): DAC channel defaults to midscale. FULL (011): DAC channel defaults to full scale. ...
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... LSB. If the magnitude of the DNL P 1 LSB, the DAC guarantees no missing codes and is monotonic. If the magnitude of the DNL R 1 LSB, the DAC output may still be monotonic. Maxim Integrated MAX5823/MAX5824/MAX5825 Offset error indicates how well the actual transfer function matches the ideal transfer function. The offset error is ...
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... CONTROL LOGIC SCL SDA ADDR0 SERIAL ADDR1 INTERFACE CLR LDAC WATCHDOG IRQ TIMER M/Z POR MAX5823 MAX5824 MAX5825 Maxim Integrated MAX5823/MAX5824/MAX5825 CODE DAC REGISTER LATCH 0 0 GATE/ CLEAR/ CLEAR/ CODE RESET LOAD RESET CHANNEL 0 POWER-DOWN DAC CONTROL LOGIC DAC CHANNEL 0 DAC CHANNEL 1 ...
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... Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I 100nF 5kI µC NOTE: BIPOLAR OPERATING CIRCUIT, ONE CHANNEL SHOWN NOTE: UNIPOLAR OPERATING CIRCUIT, ONE CHANNEL SHOWN Maxim Integrated MAX5823/MAX5824/MAX5825 5kI 5kI V V DDIO DD LDAC DAC SDA ...
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... MAX5825AAUP+ MAX5825AWP+T MAX5825BAUP+ Note: All devices are specified over the -40°C to +125°C temperature range. +Denotes a lead(Pb)–free/RoHS-compliant package Tape and reel. Chip Information PROCESS: BiCMOS Maxim Integrated MAX5823/MAX5824/MAX5825 TEMP RANGE PIN-PACkAGE -40°C to +125°C 20 TSSOP -40°C to +125°C 20 TSSOP -40°C to +125°C 20 TSSOP -40° ...
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... Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed ...