SI7860DP-E3 Vishay/Siliconix, SI7860DP-E3 Datasheet
SI7860DP-E3
Specifications of SI7860DP-E3
Related parts for SI7860DP-E3
SI7860DP-E3 Summary of contents
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... Bottom View Ordering Information: Si7860DP-T1 Si7860DP-T1-E3 (Lead (Pb)-free) Si7860DP-T1-GE3 (Lead (Pb)-free and Halogen-free) ABSOLUTE MAXIMUM RATINGS T Parameter Drain-Source Voltage Gate-Source Voltage a Continuous Drain Current (T = 150 °C) J Pulsed Drain Current Continuous Source Current (Diode Continuous) Avalanche Current ...
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... Si7860DP Vishay Siliconix SPECIFICATIONS °C, unless otherwise noted J Parameter Static Gate Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current a On-State Drain Current a Drain-Source On-State Resistance a Forward Transconductance a Diode Forward Voltage b Dynamic Total Gate Charge Gate-Source Charge Gate-Drain Charge Gate Resistance ...
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... 1000 2.00 1.75 1.50 1.25 1.00 0.75 0. 0.040 0.032 0.024 0.016 °C J 0.008 0.000 0.8 1.0 1.2 Si7860DP Vishay Siliconix C iss C oss 500 C rss Drain-to-Source Voltage (V) DS Capacitance 100 T - Junction Temperature (°C) J On-Resistance vs ...
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... Si7860DP Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 0 250 µA D 0.3 0.0 - 0.3 - 0 Temperature (°C) J Threshold Voltage 2 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0. Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0. Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations ...
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PowerPAK SO-8, (SINGLE/DUAL Notes 1. Inch will govern. 2 Dimensions exclusive of mold gate burrs. 3. Dimensions exclusive of mold flash and cutting burrs. DIM. MIN. A 0.97 A1 0.00 b ...
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... PowerPAK thermal performance see Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Sili- conix MOSFETs. Click on the PowerPAK SO-8 single in the index of this document. In this figure, the drain land pattern is given to make full contact to the drain pad on the PowerPAK package. ...
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... Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs. Click on the PowerPAK 1212-8 dual in the index of this doc- ument. The gap between the two drain pads is 24 mils. This matches the spacing of the two drain pads on the Pow- erPAK SO-8 dual package ...
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THERMAL PERFORMANCE Introduction A basic measure of a device’s thermal performance is the junction-to-case thermal resistance, Rθ junction-to-foot thermal resistance, Rθ is measured for the device mounted to an infinite heat sink and is therefore a characterization of the device ...
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AN821 Vishay Siliconix SYSTEM AND ELECTRICAL IMPACT OF PowerPAK SO-8 In any design, one must take into account the change in MOSFET r with temperature (Figure 7). DS(on) On-Resistance vs. Junction Temperature 1 1.6 I ...
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RECOMMENDED MINIMUM PADS FOR PowerPAK 0.024 (0.61) 0.026 (0.66) 0.050 (1.27) Return to Index Return to Index Document Number: 72599 Revision: 21-Jan-08 ® SO-8 Single 0.260 (6.61) 0.150 (3.81) 0.032 (0.82) Recommended Minimum Pads Dimensions in Inches/(mm) Application Note 826 ...
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ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), ...