EVAL-AD7685SDZ Analog Devices, EVAL-AD7685SDZ Datasheet - Page 21

• Manufacturer Part Number: EVAL-AD7685SDZ
• Description: Data Conversion IC Development Tools Eval Board16-Bit 250 KSPS Serial MSOP
• Manufacturer: Analog Devices
• Type: ADCr
• Series: AD7685r

Specifications of EVAL-AD7685SDZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD7685
• Interface Type: SPI
• Operating Supply Voltage: 2.3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 1

CS MODE 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7685 is connected
to an SPI-compatible digital host, which has an interrupt input,
and it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This requirement is particularly important in
applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 40, and the
corresponding timing is given in Figure 41.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time and held low until the maximum conversion time to
guarantee the generation of the BUSY signal indicator. When
the conversion is complete, SDO goes from high impedance to
low. With a pull-up on the SDO line, this transition can be used
ACQUISITION
SDO
CNV
SCK
SDI
t
SSDICNV
t
HSDICNV
CONVERSION
t
CONV
Figure 41. CS Mode 4-Wire with BUSY Indicator Serial Interface Timing
t
EN
1
Rev. C | Page 21 of 28
t
t
HSDO
DSDO
D15
2
t
CYC
as an interrupt signal to initiate the data readback controlled by
the digital host. The AD7685 then enters the acquisition phase
and powers down. The data bits are then clocked out, MSB first,
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge will allow a faster
reading rate provided it has an acceptable hold time. After the
optional 17th SCK falling edge, or SDI going high, whichever is
earlier, the SDO returns to high impedance.
D14
3
ACQUISITION
Figure 40. CS Mode 4-Wire with BUSY Indicator Connection Diagram
t
ACQ
t
SCKL
t
SCKH
15
SDI
AD7685
t
SCK
CNV
SCK
16
D1
SDO
17
D0
VIO
47kΩ
t
DIS
CS1
CONVERT
DATA IN
IRQ
CLK
DIGITAL HOST
AD7685