AD9683-250EBZ Analog Devices, AD9683-250EBZ Datasheet - Page 24

• Manufacturer Part Number: AD9683-250EBZ
• Description: Data Conversion IC Development Tools
• Manufacturer: Analog Devices
• Type: ADCr
• Series: AD9683r

Specifications of AD9683-250EBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD9683-250
• Interface Type: SPI
• Operating Supply Voltage: 1.8 V
• Description/function: Evaluation board with AD9683-250
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 149 mA
• For Use With: AD9683-250

AD9683
DIGITAL OUTPUTS
JESD204B TRANSMIT TOP LEVEL DESCRIPTION
The
JESD204B, Serial Interface for Data Converters. JESD204B is a
protocol to link the
serial interface of up to 5 Gbps link speeds. The benefits of the
JESD204B interface include a reduction in required board area
for data interface routing and the enabling of smaller packages
for converter and logic devices. The
lane interfaces.
JESD204B Overview
The JESD204B data transmit block assembles the parallel data from
the ADC into frames and uses 8B/10B encoding as well as optional
scrambling to form serial output data. Lane synchronization is
supported using special characters during the initial establishment
of the link, and additional synchronization is embedded in the
data stream thereafter. A matching external receiver is required
to lock onto the serial data stream and recover the data and clock.
For additional details on the JESD204B interface, refer to the
JESD204B standard.
The
ADC over a single link. The link is configured to use a single
pair of serial differential outputs that is called a lane. The
JESD204B specification refers to a number of parameters to
define the link, and these parameters must match between the
JESD204B transmitter
The JESD204B link is described according to the following
parameters:
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AD9683
AD9683
S = samples transmitted per single converter per frame
cycle
M = number of converters per converter device
(AD9683
L = number of lanes per converter device
(AD9683
N = converter resolution
N’ = total number of bits per sample
CF = number of control words per frame clock cycle per
converter device
CS = number of control bits/conversion sample
(configurable on the
K = number of frames per multiframe (configurable on
the AD9683)
HD = high density mode
F = octets per frame
C = control bit (overrange, overflow, underflow; available
on the AD9683)
T = tail bit (available on the AD9683)
SCR = scrambler enable/disable (configurable on the AD9683)
FCHK = checksum for the JESD204B parameters
(automatically calculated and stored in register map)
(AD9683
digital output uses the JEDEC Standard No.
JESD204B transmit block maps the output of the
value = 1)
value = 1)
AD9683
value = 1)
(AD9683
(AD9683
(AD9683
AD9683
to a digital processing device over a
(AD9683
(AD9683
output) and receiver.
value = 0)
up to two bits)
value = 2)
AD9683
value = 14)
value = 0)
(AD9683
supports single
value = 16)
Rev. 0 | Page 24 of 44
Figure 59 shows a simplified block diagram of the
JESD204B link. The
The converter data is output to SERDOUT0+/SERDOUT0−.
By default, in the AD9683, the 14-bit converter word is divided
into two octets (eight bits of data). Bit 0 (MSB) through Bit 7 are
in the first octet, and the second octet contains Bit 8 through Bit 13
(LSB) and two tail bits. The tail bits can be configured as zeros, a
pseudorandom number sequence, or control bits indicating
overrange, underrange, or valid data conditions.
The two resulting octets can be scrambled. Scrambling is
optional; however, it is available to avoid spectral peaks when
transmitting similar digital data patterns. The scrambler uses a
self synchronizing, polynomial-based algorithm defined by the
1 + x
a self-synchronizing version of the scrambler polynomial.
The two octets are then encoded with an 8B/10B encoder. The
8B/10B encoder works by taking eight bits of data (an octet) and
encoding them into a 10-bit symbol. Figure 60 shows how the
14-bit data is taken from the ADC, the tail bits are added, the two
octets are scrambled, and how the octets are encoded into two
10-bit symbols. Figure 60 illustrates the default data format.
At the data link layer, in addition to the 8B/10B encoding, the
character replacement is used to allow the receiver to monitor
frame alignment. The character replacement process occurs on the
frame and multiframe boundaries, and implementation depends
on which boundary is occurring, and if scrambling is enabled.
If scrambling is disabled, the following applies:
•
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If scrambling is enabled, the following applies:
•
•
Refer to JEDEC Standard No. 204B, July 2011 for additional
information about the JESD204B interface. Section 5.1 covers
the transport layer and data format details and Section 5.2
covers scrambling and descrambling.
If the last scrambled octet of the last frame of the multiframe
equals the last octet of the previous frame, the transmitter
replaces the last octet with the control character /A/ =
/K28.3/.
On other frames within the multiframe, if the last octet in
the frame equals the last octet of the previous frame, the
transmitter replaces the last octet with the control
character /F/ = /K28.7/.
If the last octet of the last frame of the multiframe equals
0x7C, the transmitter replaces the last octet with the
control character /A/ = /K28.3/.
On other frames within the multiframe, if the last octet
equals 0xFC, the transmitter replaces the last octet with the
control character /F/ = /K28.7/.
14
+ x
15
equation. The descrambler in the receiver should be
AD9683
uses one converter and one lane.
Data Sheet
AD9683