IS42VS16100E-10TLI-TR ISSI, Integrated Silicon Solution Inc, IS42VS16100E-10TLI-TR Datasheet

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... Integrated Silicon Solution, Inc. — www.issi.com — Rev. 00E 01/21/2011 DESCRIPTION ISSI ’s 16Mb Synchronous DRAM IS42VS16100E is organized as a 524,288-word x 16-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. PIN CONFIGURATIONS 50-Pin TSOP (Type II) VDD DQ0 ...

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... IS42VS16100E PIN CONFIGURATION package code BaLL fBga (Top View) (10 6.4 mm Body, 0.65 mm Ball pitch PIN DESCRIPTIONS a0-a10 Row address Input a0-a7 column address Input a11 Bank Select address dQ0 to dQ15 data I/o cLk System clock Input cke clock enable chip Select ...

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... IS42VS16100E PIN FUNCTIONS Pin No. Symbol Type A0-A10 Input Pin 19 A11 Input Pin 16 CAS Input Pin 34 CKE Input Pin 35 CLK Input Pin 18 CS Input Pin DQ0 to DQ Pin 12, 39, 40, 42, 43, DQ15 45, 46, 48, 49 14, 36 LDQM, Input Pin UDQM 17 RAS Input Pin 15 WE Input Pin 7, 13, 38, 44 VDDQ Power Supply Pin 1, 25 VDD Power Supply Pin 4, 10, 41, 47 ...

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... IS42VS16100E FUNCTIONAL BLOCK DIAGRAM CLK CKE COMMAND CS DECODER RAS CAS & WE CLOCK MODE A11 GENERATOR REGISTER 11 A10 SELF A9 REFRESH REFRESH A8 CONTROLLER CONTROLLER A7 A6 REFRESH A5 COUNTER ROW ADDRESS LATCH 11 4 MEMORY CELL ROW ARRAY ADDRESS 2048 BUFFER BANK SENSE AMP I/O GATE ...

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... IS42VS16100E ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Maximum Supply Voltage DD max V Maximum Supply Voltage for Output Buffer DDq max V Input Voltage in P Allowable Power Dissipation D max I Output Shorted Current cs T Operating Temperature Opr T Storage Temperature stg DC RECOMMENDED OPERATING CONDITIONS ( Commercial T = 0°C to +70°C), Industrial a Symbol Parameter Supply Voltage DD DDq V Input High Voltage ( Input Low Voltage (4) il CAPACITANCE CHARACTERISTICS Symbol Parameter C 1 Input Capacitance: CLK Input Capacitance: (A0-A11, CKE, CS, RAS, CAS, WE, LDQM, UDQM) 2.5 ...

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... IS42VS16100E DC ELECTRICAL CHARACTERISTICS Continued on next page. Symbol Parameter i Input Leakage Current il i Output Leakage Current Ol V Output High Voltage Level Oh V Output Low Voltage Level Ol DC ELECTRICAL CHARACTERISTICS Symbol Parameter i Operating Current (1,2) cc1 i Precharge Standby Current CKE ≤ V cc2p (In Power-Down Mode) I Precharge Standby Current CKE ≤ V cc2ps (In Power-Down Mode) i Active Standby Current (3) cc2n (In Non Power-Down Mode) I Active Standby Current cc2ns (In Non Power-Down Mode) i Active Standby Current cc3P (In Non Power-Down Mode) I Active Standby Current cc3Ps (In Non Power-Down Mode) i Active Standby Current ...

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... IS42VS16100E AC CHARACTERISTICS (1,2,3,6) Symbol Parameter t 3 Clock Cycle Time Access Time From CLK ( ac t CLK HIGH Level Width chi t CLK LOW Level Width Output Data Hold Time Oh t Output LOW Impedance Time Output HIGH Impedance Time Input Data Setup Time Ds t Input Data Hold Time Dh t Address Setup Time as t Address Hold Time ah t CKE Setup Time cks t CKE Hold Time ckh t CKE to CLK Recovery Delay Time cka t Command Setup Time (CS, RAS, CAS, WE, DQM Command Hold Time (CS, RAS, CAS, WE, DQM Command Period (REF to REF / ACT to ACT) ...

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... IS42VS16100E OPERATING FREQUENCY / LATENCY RELATIONSHIPS SYMBOL PARAMETER — Clock Cycle Time — Operating Frequency t CAS Latency cac t Active Command To Read/Write Command Delay Time rcD t RAS Latency ( rac rcD cac t Command Period (REF to REF / ACT to ACT Command Period (ACT to PRE) ras t Command Period (PRE to ACT Command Period (ACT[0] to ACT [1]) rrD t Column Command Delay Time ccD (READ, READA, WRIT, WRITA) ...

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... IS42VS16100E COMMANDS Active Command Read Command CLK CKE HIGH CS RAS CAS WE A0-A9 ROW A10 ROW BANK 1 A11 BANK 0 Write Command Precharge Command CLK HIGH CKE CS RAS CAS WE A0-A9 COLUMN AUTO PRECHARGE A10 NO PRECHARGE BANK 1 A11 BANK 0 Notes: 1. A8-A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com — ...

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... IS42VS16100E COMMANDS (cont.) No-Operation Command CLK CKE HIGH CS RAS CAS WE A0-A9 A10 A11 Mode Register Set Command Auto-Refresh Command CLK HIGH CKE CS RAS CAS WE A0-A9 OP-CODE A10 OP-CODE A11 OP-CODE 10 Device Deselect Command CLK CKE HIGH CS RAS CAS WE A0-A9 A10 A11 CLK HIGH CKE CS RAS CAS WE A0-A9 A10 A11 Integrated Silicon Solution, Inc. — ...

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... IS42VS16100E COMMANDS (cont.) Self-Refresh Command CLK CKE CS RAS CAS WE A0-A9 A10 A11 Clock Suspend Command CLK CKE BANK(S) ACTIVE CS NOP RAS NOP CAS NOP WE NOP A0-A9 A10 A11 Integrated Silicon Solution, Inc. — www.issi.com — Rev. 00E 01/21/2011 Power Down Command CLK CKE ALL BANKS IDLE ...

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... IS42VS16100E Mode Register Set Command (CS, RAS, CAS LOW) The IS42VS16100E product incorporates a register that defines the device operating mode. This command functions as a data input pin that loads this register from the pins A0 to A11. When power is first applied, the stipulated power-on sequence should be executed and then the IS42VS16100E should be initialized by executing a mode register set command. Note that the mode register set command can be executed only when both banks are in the idle state (i.e. deactivated). ...

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... IS42VS16100E Self-Refresh Command (CS, RAS, CAS, CKE = LOW HIGH) This command executes the self-refresh operation. The row address to be refreshed, the bank, and the refresh interval are generated automatically internally during this operation self-refresh operation is started by dropping the CKE pin from HIGH to LOW self-refresh operation continues as long as the CKE pin remains LOW and there is no need for external control of any other pins. The self-refresh operation is terminated by raising the CKE pin from LOW to HIGH. The next command cannot be executed until the device internal recovery period (t has elapsed ...

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... IS42VS16100E COMMAND TRUTH TABLE (1,2) Symbol Command (E)MRS (Extended) Mode Register Set REF Auto-Refresh (5) SREF Self-Refresh (5,6) PRE Precharge Selected Bank PALL Precharge Both Banks ACT Bank Activate (7) WRIT Write WRITA Write With Auto-Precharge READ Read (8) READA Read With Auto-Precharge BST Burst Stop (9) NOP No Operation DESL Device Deselect SBY Clock Suspend / Standby Mode ENB Data Write / Output Enable MASK Data Mask / Output Disable ...

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... IS42VS16100E OPERATION COMMAND TABLE Current State Command Operation Idle DESL No Operation or Power-Down NOP No Operation or Power-Down BST No Operation or Power-Down READ / READA Illegal WRIT/WRITA Illegal ACT Row Active PRE/PALL No Operation REF/SELF Auto-Refresh or Self-Refresh MRS Mode Register Set Row Active DESL No Operation NOP No Operation BST No Operation READ/READA Read Start WRIT/WRITA Write Start ACT ...

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... IS42VS16100E OPERATION COMMAND TABLE Current State Command Operation Write With DESL Burst Write Continues, Write Recovery And Precharge Auto-Precharge When Done NOP Burst Write Continues, Write Recovery And Precharge BST Illegal READ/READA Illegal WRIT/WRITA Illegal ACT Illegal PRE/PALL Illegal REF/SELF Illegal MRS Illegal Row Precharge DESL No Operation, Idle State After t NOP No Operation, Idle State After t BST No Operation, Idle State After t READ/READA Illegal WRIT/WRITA ...

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... A8,A9 = don’t care. Integrated Silicon Solution, Inc. — www.issi.com — Rev. 00E 01/21/2011 (1,2) Has Elapsed Dal Has Elapsed Dal Has Elapsed Dal (10) (10) (10) (10) Has Elapsed rp Has Elapsed rp Has Elapsed rp Has Elapsed mcD Has Elapsed mcD Has Elapsed mcD has elapsed. Also note that the IS42VS16100E will enter the pre- rcD 1-800-379-4774 CS RAS CAS WE A11 A10 A 9- ...

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... IS42VS16100E CKE RELATED COMMAND TRUTH TABLE Current State Operation Self-Refresh Undefined Self-Refresh Recovery Self-Refresh Recovery Illegal (2) Illegal (2) Self-Refresh Self-Refresh Recovery Idle State After t Idle State After t Illegal Illegal Power-Down on the Next Cycle Power-Down on the Next Cycle Illegal Illegal Clock Suspend Termination on the Next Cycle Clock Suspend Power-Down Undefined Power-Down Mode Termination, Idle After That Termination Power-Down Mode Both Banks Idle No Operation See the Operation Command Table Bank Active Or Precharge Auto-Refresh Mode Register Set See the Operation Command Table See the Operation Command Table See the Operation Command Table ...

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... IS42VS16100E TWO BANKS OPERATION COMMAND TRUTH TABLE Operation CS RAS CAS WE A11 A10 A 9-A0 BANK 0 B ANK 1 BANK 0 B ANK 1 DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF MRS Notes HIGH level input, L: LOW level input, X: HIGH or LOW level input, RA: Row Address, CA: Column Address 2. The device state symbols are interpreted as follows: I Idle (inactive state) A Row Active State R Read W Write RP Read With Auto-Precharge WP Write With Auto-Precharge Any Any State 3. CA: A8,A9 = don’t care. ...

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... IS42VS16100E SIMPLIFIED STATE TRANSITION DIAGRAM WRIT CKE_ CKE CLOCK WRITA SUSPEND CKE_ CKE POWER APPLIED Automatic transition following the completion of command execution. Transition due to command input. 20 (One Bank Operation) SREF entry MRS MODE REF IDLE REGISTER SET CKE_ CKE ACT CKE_ BANK BST ACTIVE WRIT WRITA ...

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... See the table on the next page for details on setting the mode register. Burst Type The burst data order during a read or write operation is stipulated by the burst type, which can be set by the mode register set command. The IS42VS16100E product supports sequential mode and interleaved mode burst type settings. See the table on the next page for details on setting the mode register. See the “Burst Length and Column Address Sequence” item for details on DQ data orders in these modes. ...

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... IS42VS16100E MODE REGISTER A 11 A10 RITE MODE LT M ODE M11 M10 Note: Other values for these bits are reserved. 22 Address Bus (Ax) Mode Register (Mx Burst Length 0 Burst Type Latency Mode 0 Write Mode 0 Burst Read & Single Write 0 Burst Read & Burst Write Integrated Silicon Solution, Inc. — www.issi.com — Sequential Interleaved Reserved Reserved Reserved Reserved Reserved Reserved Full Page Reserved M3 Type ...

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... IS42VS16100E BURST LENGTH AND COLUMN ADDRESS SEQUENCE Column Address Burst Length Full Page n n (256) Notes: 1. The burst length in full page mode is 256. Integrated Silicon Solution, Inc. — www.issi.com — Rev. 00E 01/21/2011 Address Sequence Sequential 0 0-1 1 1-0 0 0-1-2-3 1 1-2-3-0 0 2-3-0-1 1 3-0-1-2 0 0-1-2-3-4-5-6-7 ...

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... IS42VS16100E BANK SELECT AND PRECHARGE ADDRESS ALLOCATION Row X0 — X1 — X2 — X3 — X4 — X5 — X6 — X7 — X8 — X9 — X10 0 1 Command) X11 0 1 Column Y0 — Y1 — Y2 — Y3 — Y4 — Y5 — Y6 — Y7 — Y8 — Y9 — Y10 0 1 Y11 Row Address Row Address Row Address Row Address Row Address Row Address Row Address Row Address ...

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... IS42VS16100E Burst Read The read cycle is started by executing the read command. The address provided during read command execution is used as the starting address. First, the data corresponding to this address is output in synchronization with the clock signal after the CAS latency period. Next, data corresponding to an address generated automatically by the device is output in synchronization with the clock signal. The output buffers go to the LOW impedance state CAS latency minus one cycle after the read command, and go to the HIGH impedance state automatically after the last data is output. However, the case where the burst length CLK COMMAND READ A0 UDQM LDQM DQ8-DQ15 DQ0-DQ 7 READ (CA=A, BANK 0) CAS latency = 3, burst length = 4 Burst Write The write cycle is started by executing the command ...

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... IS42VS16100E Read With Auto-Precharge The read with auto-precharge command first executes a burst read operation and then puts the selected bank in the precharged state automatically. After the precharge completes, the bank goes to the idle state. Thus this command performs a read command and a precharge command in a single operation. During this operation, the delay period (t last burst data output and the start of the precharge opera- tion differs depending on the CAS latency setting. When the CAS latency setting is two, the precharge opera- tion starts on one clock cycle before the last burst data is output (t = –1). When the CAS latency setting is ...

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... IS42VS16100E Write With Auto-Precharge The write with auto-precharge command first executes a burst write operation and then puts the selected bank in the precharged state automatically. After the precharge completes the bank goes to the idle state. Thus this command performs a write command and a precharge command in a single operation. During this operation, the delay period (t last burst data input and the completion of the precharge operation differs depending on the CAS latency setting. The delay ( plus one CLK period. That is, the Dal rp precharge operation starts one clock period after the last burst data input. CLK COMMAND WRITE WRITE WITH AUTO-PRECHARGE ...

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... IS42VS16100E Interval Between Read Command A new command can be executed while a read cycle is in progress, i.e., before that cycle completes. When the second read command is executed, after the CAS latency has elapsed, data corresponding to the new read command is output in place of the data due to the previous read command. CLK COMMAND READ A0 DQ READ (CA=A, BANK 0) READ (CA=B, BANK 0) CAS latency = 2, burstlength = 4 Interval Between Write Command A new command can be executed while a write cycle is in progress, i ...

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... IS42VS16100E Interval Between Write and Read Commands A new read command can be executed while a write cycle is in progress, i.e., before that cycle completes. Data corresponding to the new read command is output after the CAS latency has elapsed from the point the new read command was executed. The DQn pins must be placed in the HIGH impedance state at least one cycle before data is output during this operation. CLK t CCD COMMAND WRITE A0 READ WRITE (CA=A, BANK 0) CAS latency = 2, burstlength = 4 CLK t CCD COMMAND WRITE A0 READ WRITE (CA=A, BANK 0) CAS latency = 3, burstlength = 4 Integrated Silicon Solution, Inc. — ...

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... IS42VS16100E Interval Between Read and Write Commands A read command can be interrupted and a new write command executed while the read cycle is in progress, i.e., before that cycle completes. Data corresponding to the new write command can be input at the point new write command is executed. To prevent collision between input and output data at the DQn pins during this operation, the CLK COMMAND READ A0 U/LDQM HI-Z DQ READ (CA=A, BANK 0) CAS latency = 2, 3, burstlength = 4 30 output data must be masked using the U/LDQM pins. The interval (t ) between these commands must be at least ccD one clock cycle. ...

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... IS42VS16100E Precharge The precharge command sets the bank selected by pin A11 to the precharged state. This command can be executed at a time t following the execution of an active command ras to the same bank. The selected bank goes to the idle state at a time t following the execution of the precharge rp command, and an active command can be executed again for that bank. If pin A10 is low when this command is executed, the bank selected by pin A11 will be precharged, and if pin A10 is HIGH, both banks will be precharged at the same time. This input to pin A11 is ignored in the latter case ...

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... IS42VS16100E Write Cycle Interruption Using the Precharge Command A write cycle can be interrupted by the execution of the precharge command before that cycle completes. The delay time (t ) from the precharge command to the point wDl where burst input is invalid, i.e., the point where input data is no longer written to device internal memory is zero clock cycles regardless of the CAS. To inhibit invalid write, the DQM signal must be asserted HIGH with the precharge command. This precharge command and burst write command must be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of dual bank operation. CLK COMMAND WRITE A0 DQM ...

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... The IS42VS16100E can output data continuously from the burst start address (a) to location a+255 during a read cycle in which the burst length is set to full page. The IS42VS16100E repeats the operation starting at the 256th cycle with the data output returning to location (a) and continuing with a+1, a+2, a+3, etc. A burst stop command must be executed to terminate this cycle. A ...

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... IS42VS16100E Write Cycle (Full Page) Interruption Using the Burst Stop Command The IS42VS16100E can input data continuously from the burst start address (a) to location a+255 during a write cycle in which the burst length is set to full page. The IS42VS16100E repeats the operation starting at the 256th cycle with data input returning to location (a) and continuing with a+1, a+2, a+3, etc. A burst stop command must be executed to terminate this cycle. A precharge command CLK COMMAND WRITE READ (CA=A, BANK 0) Burst Data Interruption Using the U/LDQM Pins (Read Cycle) Burst data output can be temporarily interrupted (masked) during a read cycle using the U/LDQM pins. Regardless of the CAS latency, two clock cycles (t U/LDQM pins goes HIGH, the corresponding outputs go to the HIGH impedance state ...

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... Cycle) Burst data input can be temporarily interrupted (muted ) during a write cycle using the U/LDQM pins. Regardless of the CAS latency, as soon as one of the U/LDQM pins goes HIGH, the corresponding externally applied input data will no longer be written to the device internal circuits. Subsequently, the corresponding input continues to be muted as long as that U/LDQM pin remains HIGH. The IS42VS16100E will revert to accepting input as soon as CLK COMMAND UDQM LDQM DQ8-DQ15 DQ0-DQ7 WRITE (CA=A, BANK 0) ...

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... COMMAND ACT 0 BANK ACTIVE (BANK 0) CAS latency = 3 Clock Suspend When the CKE pin is dropped from HIGH to LOW during a read or write cycle, the IS42VS16100E enters clock suspend mode on the next CLK rising edge. T his command reduces the device power dissipation by stopping the device internal clock. Clock suspend mode continues as long as the CKE pin remains low. In this state, all inputs other than CKE pin are invalid and no other commands can be executed. Also, the device internal states are maintained ...

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... IS42VS16100E OPERATION TIMING EXAMPLE Power-On Sequence, Mode Register Set Cycle CLK t CHI HIGH CKE RAS CAS A0- A10 BANK 0 & 1 A11 DQM HIGH DQ WAIT TIME t RP T=100 µs < > PALL CAS latency = 2, 3 Integrated Silicon Solution, Inc. — www.issi.com — Rev. 00E 01/21/2011 T3 T10 T17 < > < > < REF REF ...

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... IS42VS16100E Power-Down Mode Cycle CLK t CHI CKS CK CL CKE t CKA RAS CAS A0- A10 BANK 0 & 1 BANK A11 BANK 1 BANK 0 DQM < > PRE < > PALL CAS latency = CKS POWER DOWN MODE < > SBY Integrated Silicon Solution, Inc. — www.issi.com — Tn Tn+1 Tn+2 Tn+3 t CKH t CKA ...

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... IS42VS16100E Auto-Refresh Cycle CLK t CHI CKS CK CL CKE RAS CAS A0- A10 BANK 0 & 1 A11 DQM < > PALL CAS latency = 2, 3 Integrated Silicon Solution, Inc. — www.issi.com — Rev. 00E 01/21/2011 < > < > < REF REF 1-800-379-4774 Tm Tn Tn+1 ROW ROW BANK 1 BANK RAS ...

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... IS42VS16100E Self-Refresh Cycle CLK t CHI CKS CK CL CKE t CKA RAS CAS A0- A10 BANK 0 & 1 A11 DQM < > PALL CAS latency = 2, 3 Note 1: A8,A9 = Don’t Care Tm CKS CKS EXIT SELF REFRESH MODE SELF REFRESH < > SELF Integrated Silicon Solution, Inc. — www.issi.com — ...

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... IS42VS16100E Read Cycle CLK t CHI CKS CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM DQ t RCD t RAS t RC < > < ACT READ CAS latency = 2, burstlength = 4 Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com — Rev. 00E 01/21/2011 T3 T4 ...

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... IS42VS16100E Read Cycle / Auto-Precharge CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW A10 ROW BANK 1 A11 BANK 0 DQM DQ t RCD t RAS t RC < > < > ACT READA CAS latency = 2, burstlength = 4 Note 1: A8,A9 = Don’t Care (1) COLUMN m AUTO PRE BANK 1 BANK QMD m+1 OUT ...

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... IS42VS16100E Read Cycle / Full Page CLK t CHI t t CKS CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 0 A11 DQM DQ t RCD t RAS t RC (BANK 0) < > < ACT 0 READ0 CAS latency = 2, burstlength = full page Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com — ...

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... IS42VS16100E Read Cycle / Ping-Pong Operation (Bank Switching CLK t CHI t t CKS CKE t CKA RAS CAS A0-A9 ROW A10 ROW BANK 0 A11 DQM DQ t RRD (BANK RCD (BANK 0) t RAS (BANK (BANK 0) < > ACT 0 CAS latency = 2, burstlength = 2 Note 1: A8,A9 = Don’t Care (1) (1) COLUMN ROW COLUMN AUTO PRE ...

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... IS42VS16100E Write Cycle CLK t CHI CKS CK CL CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 1 BANK 0 DQM DQ t RCD t RAS t RC < > ACT CAS latency = 2, burstlength = 4 Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com — Rev. 00E 01/21/2011 T3 T4 ...

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... IS42VS16100E Write Cycle / Auto-Precharge CLK t CHI CKS CK CL CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 1 BANK 0 DQM DQ t RCD t RAS t RC < > ACT CAS latency = 2, burstlength = 4 Note 1: A8,A9 = Don’t Care (1) COLUMN m AUTO PRE BANK 1 BANK m+1 D m DAL < ...

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... IS42VS16100E Write Cycle / Full Page CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW A10 ROW BANK 0 A11 DQM DQ t RCD t RAS t RC < > ACT 0 CAS latency = 2, burst length = full page Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com — Rev. 00E ...

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... IS42VS16100E Write Cycle / Ping-Pong Operation CLK t CHI t t CKS CKE t CKA RAS CAS A0-A9 ROW A10 ROW BANK 0 A11 DQM DQ t RRD (BANK RCD (BANK 0) t RAS (BANK (BANK 0) < > ACT 0 CAS latency = 2, burst length = 2 Note 1: A8,A9 = Don’t Care (1) COLUMN ROW AUTO PRE ROW ...

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... IS42VS16100E Read Cycle / Page Mode CLK t CHI CKS CK CL CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 1 BANK 0 DQM DQ t RCD t RAS t RC < > ACT CAS latency = 2, burst length = 2 Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com — Rev. 00E ...

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... IS42VS16100E Read Cycle / Page Mode; Data Masking CLK t CHI t t CKS CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 1 BANK 0 DQM DQ t RCD t RAS t RC < > ACT CAS latency = 2, burst length = 2 Note 1: A8,A9 = Don’t Care (1) (1) COLUMN m COLUMN n NO PRE NO PRE NO PRE BANK 1 ...

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... IS42VS16100E Write Cycle / Page Mode CLK t CHI CKS CK CL CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM DQ t RCD t RAS t RC < > ACT CAS latency = 2, burst length = 2 Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com — Rev. 00E ...

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... IS42VS16100E Write Cycle / Page Mode; Data Masking CLK t CHI t t CKS CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM DQ t RCD t RAS t RC < > ACT CAS latency = 2, burst length = 2 Note 1: A8,A9 = Don’t Care (1) (1) COLUMN m COLUMN n NO PRE NO PRE BANK 1 BANK 1 ...

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... IS42VS16100E Read Cycle / Clock Suspend CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM DQ t RCD t RAS t RC < > ACT 0 CAS latency = 2, burst length = 2 Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com — Rev. 00E ...

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... IS42VS16100E Write Cycle / Clock Suspend CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM DQ t RCD t RAS t RC < > ACT CAS latency = 2, burst length = 2 Note 1: A8,A9 = Don’t Care CKS CKH (1) COLUMN m AUTO PRE NO PRE BANK 1 BANK m+1 ...

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... IS42VS16100E Read Cycle / Precharge Termination CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 0 DQM DQ t RCD t RAS t RC < > ACT 0 CAS latency = 2, burst length = 4 Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com — Rev. 00E 01/21/2011 ...

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... IS42VS16100E Write Cycle / Precharge Termination CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK DQM DQ t RCD t RAS t RC < > ACT 0 CAS latency = 2, burst length = 4 Note 1: A8,A9 = Don’t Care (1) COLUMN m NO PRE BANK BANK 0 BANK 0m < > < ...

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... IS42VS16100E Read Cycle / Byte Operation CLK t CHI CKS CK CL CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 1 BANK 0 UDQM LDQM DQ8-15 DQ0-7 t RCD t RAS t RC < > ACT CAS latency = 2, burst length = 4 Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com — ...

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... IS42VS16100E Write Cycle / Byte Operation CLK t CHI CKS CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 1 BANK 0 UDQM LDQM DQ8-15 DQ0-7 t RCD t RAS t RC < > ACT CAS latency = 2, burst length = 4 Note 1: A8,A9 = Don’t Care (1) COLUMN m AUTO PRE NO PRE BANK 1 BANK m+1 D m+3 ...

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... IS42VS16100E Read Cycle, Write Cycle / Burst Read, Single Write CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW A10 ROW BANK 1 A11 BANK 0 DQM DQ t RCD t RAS t RC < > ACT CAS latency = 2, burst length = 4 Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com — ...

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... IS42VS16100E Read Cycle CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW A10 ROW BANK 1 A11 BANK 0 DQM DQ t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 4 Note 1: A8,A9 = Don’t Care (1) COLUMN m NO PRE BANK 1 BANK QMD OUT CAC < > READ Integrated Silicon Solution, Inc. — ...

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... IS42VS16100E Read Cycle / Auto-Precharge CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW A10 ROW BANK 1 A11 BANK 0 DQM DQ t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 4 Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com — Rev. 00E ...

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... IS42VS16100E Read Cycle / Full Page CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 0 A11 DQM DQ t RCD (BANK 0) t RAS (BANK (BANK 0) < > ACT 0 CAS latency = 3, burst length = full page Note 1: A8,A9 = Don’t Care (1) COLUMN NO PRE BANK 0m+1 OUT OUT ...

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... IS42VS16100E Read Cycle / Ping Pong Operation (Bank Switching CLK t CHI CKS CK CL CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 0 A11 DQM DQ t RRD (BANK RCD (BANK 0) t RAS (BANK (BANK 0) < > ACT 0 CAS latency = 3, burst length = 2 Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com — ...

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... IS42VS16100E Write Cycle CLK t CHI t t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM DQ t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 4 Note 1: A8,A9 = Don’t Care (1) COLUMN NO PRE BANK 1 BANK m+2 D m DPL < > WRIT Integrated Silicon Solution, Inc. — ...

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... IS42VS16100E Write Cycle / Auto-Precharge CLK t CHI t t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM DQ t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 4 Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com — Rev. 00E ...

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... IS42VS16100E Write Cycle / Full Page CLK t CHI CKS CK CL CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 0 A11 DQM DQ t RCD t RAS t RC < > ACT 0 CAS latency = 3, burst length = full page Note 1: A8,A9 = Don’t Care T259 (1) COLUMN NO PRE BANK 0m+1 D 0m < > WRIT0 Integrated Silicon Solution, Inc. — ...

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... IS42VS16100E Write Cycle / Ping-Pong Operation (Bank Switching CLK t CHI CKS CK CL CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 0 A11 DQM DQ t RRD (BANK RCD (BANK 0) t RAS (BANK (BANK 0) < > ACT 0 CAS latency = 3, burst length = 4 Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com — ...

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... IS42VS16100E Read Cycle / Page Mode CLK t CHI CKS CK CL CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 1 BANK 0 DQM DQ t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 2 Note 1: A8,A9 = Don’t Care (1) (1) COLUMN m COLUMN n NO PRE NO PRE BANK 1 BANK 1 BANK 0 ...

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... IS42VS16100E Read Cycle / Page Mode; Data Masking CLK t CHI CKS CK CL CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 1 BANK 0 DQM DQ t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 2 Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com — Rev. 00E ...

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... IS42VS16100E Write Cycle / Page Mode CLK t CHI t t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 0 A11 DQM DQ t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 2 Note 1: A8,A9 = Don’t Care (1) (1) COLUMN m COLUMN n NO PRE NO PRE BANK 1 BANK 1 BANK 0 BANK 0 ...

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... IS42VS16100E Write Cycle / Page Mode; Data Masking CLK t CHI t t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 t t BANK BANK 1 A11 BANK 0 BANK DQM RCD t RAS t RC < > < ACT WRIT CAS latency = 3, burst length = 2 Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com — ...

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... IS42VS16100E Read Cycle / Clock Suspend CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM DQ t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 2 Note 1: A8,A9 = Don’t Care CKS (1) COLUMN m AUTO PRE NO PRE BANK 1 BANK QMD OUT ...

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... IS42VS16100E Write Cycle / Clock Suspend CLK t CHI CKS CK CL CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM DQ t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 2 Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com — Rev. 00E ...

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... IS42VS16100E Read Cycle / Precharge Termination CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 0 DQM DQ t RCD t RAS t RC < > ACT 0 CAS latency = 3, burst length = 2 Note 1: A8,A9 = Don’t Care (1) COLUMN m BANK PRE BANK 0 BANK QMD OUT CAC < > < ...

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... IS42VS16100E Write Cycle / Precharge Termination CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 0 DQM DQ t RCD t RAS t RC < > ACT 0 CAS latency = 3, burst length = 4 Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com — Rev. 00E 01/21/2011 ...

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... IS42VS16100E Read Cycle / Byte Operation CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 1 BANK 0 UDQM LDQM DQ8-15 DQ0-7 t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 4 Note 1: A8,A9 = Don’t Care (1) COLUMN m AUTO PRE NO PRE BANK 1 BANK QMD ...

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... IS42VS16100E Write Cycle / Byte Operation CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 1 BANK 0 UDQM LDQM DQ8-15 DQ0-7 t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 4 Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com — ...

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... IS42VS16100E Read Cycle, Write Cycle / Burst Read, Single Write CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM RAS t RC < > ACT CAS latency = 3, burst length = 2 Note 1: A8,A9 = Don’t Care (1) COLUMN m NO PRE BANK 1 BANK QMD m+1 OUT OUT ...

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... Integrated Silicon Solution, Inc. — www.issi.com — Rev. 00E 01/21/2011 Order Part No. 7.5 IS42VS16100E-75TL IS42VS16100E-75BL 10 IS42VS16100E-10TL IS42VS16100E-10BL Order Part No. 7.5 IS42VS16100E-75TLI IS42VS16100E-75BLI 10 IS42VS16100E-10TLI IS42VS16100E-10BLI 1-800-379-4774 Package 400-mil TSOP II, Lead-free 60-ball BGA, Lead-free 400-mil TSOP II, Lead-free 60-ball BGA, Lead-free Package 400-mil TSOP II, Lead-free 60-ball BGA, Lead-free 400-mil TSOP II, Lead-free 60-ball BGA, Lead-free ...

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... IS42VS16100E 80 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00E 01/21/2011 ...

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... IS42VS16100E Integrated Silicon Solution, Inc. — www.issi.com — Rev. 00E 01/21/2011 1-800-379-4774 81 ...