IS62WV1288BLL-55QLI ISSI, Integrated Silicon Solution Inc, IS62WV1288BLL-55QLI Datasheet - Page 8

• Manufacturer Part Number: IS62WV1288BLL-55QLI
• Description: IC SRAM 1MBIT 55NS 32SOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS62WV1288BLL-55QLI

• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Memory Size: 1M (128K x 8)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-SOP
• Density: 1Mb
• Access Time (max): 55ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: SOP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 8mA
• Operating Supply Voltage (min): 2.5V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Word Size: 8b
• Number Of Words: 128K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS62WV1288ALL, IS62WV1288BLL, IS65WV1288BLL
8
WRITE CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH, and WE LOW. All signals must be in valid states to initiate a Write, but any one can
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS1/CS2 Controlled, OE = HIGH or LOW)
Symbol
ADDRESS
t
t
t
t
t
t
t
t
t
t
V
go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
Wc
scs1/
AW
hA
sA
PWe
sd
hd
hzWe
LzWe
dd
-0.2V/V
(3)
t
(3)
DOUT
scs2
CS1
CS2
DIN
WE
dd
Parameter
Write Cycle Time
CS1/CS2 to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
-0.3V and output loading specified in Figure 1.
t
DATA UNDEFINED
SA
Integrated Silicon Solution, Inc. — www.issi.com —
t
Min.
AW
45
35
35
20
—
35
0
0
5
0
t
45 ns
HZWE
t
t
Max.
SCS2
SCS1
—
—
—
—
—
—
—
—
20
—
t
WC
t
PWE
(1,2)
HIGH-Z
(Over Operating Range)
Min. Max.
45
45
40
25
—
t
55
0
0
0
5
SD
55 ns
DATA-IN VALID
—
—
—
—
—
—
—
—
20
—
t
HA
t
t
LZWE
HD
Min. Max.
50
30
—
0
0
0
5
70
60
60
70 ns
20
—
—
—
—
—
—
—
—
—
1-800-379-4774
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11/12/08
Rev. E