IS42S16400D-7TL-TR ISSI, Integrated Silicon Solution Inc, IS42S16400D-7TL-TR Datasheet - Page 10
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IS42S16400D-7TL-TR
Manufacturer Part Number
IS42S16400D-7TL-TR
Description
IC SDRAM 64MBIT 143MHZ 54TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Datasheet
1.IS42S16400D-7TL.pdf
(57 pages)
Specifications of IS42S16400D-7TL-TR
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
64M (4M x 16)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-TSOP II
Organization
4Mx16
Density
64Mb
Address Bus
14b
Access Time (max)
6/5.4ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
100mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
IS42S16400D
TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK m
NOTE:
10
3. Current state definitions:
1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (Truth Table - CKE) and after t
2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown
4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
CURRENT STATE
Any
Idle
Row
Activating,
Active, or
Precharging
Read
(Auto
Precharge
Disabled)
Write
(Auto
Precharge
Disabled)
Read
(With Auto
Precharge)
Write
(With Auto
Precharge)
state was self refresh).
are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are
covered in the notes below.
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when t
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when t
Read w/Auto
Write w/Auto
Row Active: A row in the bank has been activated, and t
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
Idle: The bank has been precharged, and t
accesses are in progress.
Once t
met. Once t
COMMAND (ACTION)
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
Any Command Otherwise Allowed to Bank m
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
RP
is met, the bank will be in the idle state.
RP
is met, the bank will be in the idle state.
(9)
(9)
(9)
(9)
RP
has been met.
RCD
has been met. No data bursts/accesses and no register
Integrated Silicon Solution, Inc. — www.issi.com
(7)
(7,12)
(7,8,16)
(7)
(7,11)
(7,8,15)
(7,10)
(7,8,14)
(7,13)
(7,8,17)
XSR
(1-6)
has been met (if the previous
CS RAS CAS WE
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
RP
RP
has been met.
has been
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
11/21/07
Rev. E
X
H
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L