LFE3-95EA-V-EVN Lattice, LFE3-95EA-V-EVN Datasheet - Page 13

• Manufacturer Part Number: LFE3-95EA-V-EVN
• Description: Programmable Logic IC Development Tools LatticeECP3-95EA Video Protocol Board
• Manufacturer: Lattice
• Type: FPGAr

Specifications of LFE3-95EA-V-EVN

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: LFE3-95E-7FN1156C
• Interface Type: DVI
• Operating Supply Voltage: 12 V
• Description/function: LatticeECP3 Video protocol board
• Factory Pack Quantity: 1

Table 18. SERDES PCI Express Interconnections
Figure 6. Block Diagram of the DisplayPort Video Interface
Table 17 shows the pin connections of the DisplayPort video interface.
Table 17. DisplayPort Connections (J3 and J4)
Quad B (PCI Express x4)
This board is equipped to communicate directly as an add-on card to a PCI Express host. It is designed with edge-
fingers (CN1) to fit directly into a x1 host receptacle. Power can be supplied directly from the PCI Express host via
the edge-finger connections.
All channels of Quad 1 are connected to the PCI Express Edge connector (CN1) for implementing a PCI Express
x4 interface. The dedicated reference clock input pins and a reset control signal are also connected to the PCI
Express edge connector.
DisplayPort
Tx (J4)
DisplayPort
Rx (J3)
PCI Express
PERp0
PERn0
Name
Connector
DisplayPort
Rx (J3)
PWR_OUT
ML0_N_IN
ML1_N_IN
HPD_OUT
ML0_P_IN
ML1_P_IN
CONFIG1
CONFIG2
AUX_P
AUX_N
PCI Express
Pin #
A16
A17
ML0_[P:N]_OUT
ML1_[P:N]_OUT
AUX_[P:N]
HPD_IN
ML0_[P:N]_IN
ML1_[P:N]_IN
AUX_[P:N]
HPD_OUT
3.3V
1K
3.3V Voltage
Pin Name
1M
1M
Regulator
0.1uF
0.1uF
PCSB_HDOUTP0
PCSB_HDOUTN0
1K
(U19)
0.1uF
0.1uF
0.1uF
0.1uF
LatticeECP3
Pin Name
49.9
49.9
0.01uF
100K
e
5.0V
n
100
100
a
b
e l
1 and 2
4 and 6
15 and 17
18
10 and 12
7 and 8
15 and 17
18
AK19
AK18
AL19
AL18
G17
N27
N28
C31
LatticeECP3
LatticeECP3
LatticeECP3 Video Protocol Board – Revision C
Quad 0
Quad 0
AP17
AN17
(U30)
Pin #
Pin #
CH2
CH3
13
AP19
AN19
AP18
AN18
R26
R25
C32
J16
Coupling
e
100
0.01uF
100
n
LatticeECP3 Pin Name
PCSA_HDOUT[P:N]2
PCSA_HDOUT[P:N]3
PR31[A:B]
PT143B
PCSA_HDIN[P:N]2
PCSA_HDIN[P:N]3
PR22[A:B]
PT145B
5.0V
a
C365
C366
b
AC
e l
3.3V Voltage
100K
49.9
49.9
Regulator
(U23)
0.1uF
0.1uF
Receiver differential pair, Lane 0
3.3V
0.1uF
0.1uF
0.1uF
0.1uF
1K
PCI Express Pin Description
100K
100K
1K
AP19, AN19
AL18, AK18
R26, R25
C32
AL19, AK19
AL18, AK18
N27, N28
C31
ML0_P_OUT
ML0_N_OUT
ML1_P_OUT
ML1_N_OUT
AUX_P
AUX_N
HPD_OUT
CONFIG1
CONFIG2
PWR_OUT
DisplayPort
LatticeECP3 Pin #
Tx (J4)
User’s Guide