MAX17050EVKIT# Maxim Integrated, MAX17050EVKIT# Datasheet - Page 45

• Manufacturer Part Number: MAX17050EVKIT#
• Description: Power Management IC Development Tools MAX17050 Eval Kit
• Manufacturer: Maxim Integrated
• Type: Voltage Protectionr
• Series: MAX17047, MAX17050r

Specifications of MAX17050EVKIT#

• Rohs: yes
• Product: Evaluation Kits
• Tool Is For Evaluation Of: MAX17050
• Input Voltage: 2.5 V to 4.5 V
• Interface Type: I2C
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Part # Aliases: 90-BT07K#D00
• For Use With: MAX17050

monitoring the acknowledge bit for presence of the
device. More complex formats such as the write Data,
read Data, and Function command protocols write data,
read data, and execute device-specific operations,
respectively. All bytes in each command format require
the slave or the host system to return an Acknowledge bit
before continuing with the next byte. Each function com-
mand definition outlines the required transaction format.
Table 6
Write: S SAddr W A MAddr A DataL A DataH A P
A write transaction transfers 1 or more data bytes to the
device. The data transfer begins at the memory address
supplied in the MAddr byte. Control of the SDA signal is
retained by the master throughout the transaction, except
for the Acknowledge cycles.
A read transaction transfers one or more words from the
IC. Read transactions are composed of two parts, a write
portion followed by a read portion, and are therefore
inherently longer than a write transaction. The write por-
tion communicates the starting point for the read opera-
tion. The read portion follows immediately, beginning with
a Repeated START, Slave Address with R/W set to a 1.
Control of SDA is assumed by the IC beginning with the
Slave Address Acknowledge cycle. Control of the SDA
signal is retained by the device throughout the transac-
tion, except for the Acknowledge cycles. The master
indicates the end of a read transaction by responding
Table 6. 2-Wire Protocol Key
Maxim Integrated
Read: S SAddr W A MAddr A Sr SAddr R A DataL A DataH N P
MAddr
SAddr
FCmd
KEY
Data
A
N
S
applies to the transaction formats.
write Portion
START bit
Slave Address
(7 bit)
Function Command
byte
Memory Address
byte
Data byte written by
Master
Acknowledge bit—
Master
No Acknowledge—
Master
DESCRIPTION
Basic Transaction Formats
read Portion
KEY
Data
Sr
W
R
A
N
P
Repeated START
R/W bit = 0
R/W bit = 1
STOP bit
Data byte returned
by Slave
Acknowledge bit—
Slave
No Acknowledge—
Slave
DESCRIPTION
ModelGauge m3 Fuel Gauge
to the last byte it requires with a No Acknowledge. This
signals the device that control of SDA is to remain with
the master following the Acknowledge clock.
The write Data protocol is used to write to register and
shadow RAM data to the IC starting at memory address
MAddr. Data0 represents the data written to MAddr,
Data1 represents the data written to MAddr + 1, and
DataN represents the last data byte written to MAddr +
N. The master indicates the end of a write transaction by
sending a STOP or Repeated START after receiving the
last acknowledge bit:
A DataH1 A … DataLN A DataHN A P
The MSb of the data to be stored at address MAddr
can be written immediately after the MAddr byte is
acknowledged. Because the address is automatically
incremented after the least significant bit (LSb) of each
byte is received by the device, the MSb of the data at
address MAddr + 1 can be written immediately after the
acknowledgment of the data at address MAddr. If the
bus master continues an autoincremented write transac-
tion beyond address FFh, the device ignores the data.
Data is also ignored on writes to read-only addresses
but not reserved addresses. Do not write to reserved
address locations.
The read data protocol is used to read register and
shadow RAM data from the device starting at memory
address specified by MAddr. Data0 represents the data
byte in memory location MAddr, Data1 represents the
data from MAddr + 1, and DataN represents the last byte
read by the master:
DataH0 A DataL1 A DataH1 A …DataLN N DataHN N P
Data is returned beginning with the most significant bit
(MSb) of the data in MAddr. Because the address is
automatically incremented after the LSb of each byte
is returned, the MSb of the data at address MAddr +
1 is available to the host system immediately after the
acknowledgment of the data at address MAddr. If the
bus master continues to read beyond address FFh, the
device outputs data values of FFh. Addresses labeled
Reserved in the memory map return undefined data. The
bus master terminates the read transaction at any byte
boundary by issuing a No Acknowledge followed by a
STOP or Repeated START.
MAX17047/MAX17050
S SAddr W A MAddr A DataL0 A DataH0 A DataL1
S SAddr W A MAddr A Sr SAddr R A DataL0 A
Write Data Protocol
Read Data Protocol
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