IS42S16400D-6TLI-TR ISSI, Integrated Silicon Solution Inc, IS42S16400D-6TLI-TR Datasheet - Page 11

• Manufacturer Part Number: IS42S16400D-6TLI-TR
• Description: IC SDRAM 64MBIT 166MHZ 54TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS42S16400D-6TLI-TR

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 54-TSOP II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS42S16400D
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
11/21/07
10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled
8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command when its burst has been inter-
9. Burst in bank n continues as initiated.
and READs or WRITEs with auto precharge disabled.
rupted by bank m’s burst.
READ on bank n, CAS latency later (Consecutive READ Bursts).
the READ on bank n when registered (READ to WRITE). DQM should be used one clock prior to the WRITE command to prevent
bus contention.
the WRITE on bank n when registered (WRITE to READ), with the data-out appearing CAS latency later. The last valid WRITE to
bank n will be data-in registered one clock prior to the READ to bank m.
the WRITE on bank n when registered (WRITE to WRITE). The last valid WRITE to bank n will be data-in registered one clock
prior to the READ to bank m.
READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Fig CAP 1).
READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to bank m is registered (Fig CAP 2).
WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after
t
one clock prior to the READ to bank m (Fig CAP 3).
WRITE on bank n when registered. The PRECHARGE to bank n will begin after t
to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Fig CAP 4).
WR
is met, where t
WR
begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered
WR
is met, where t WR begins when the WRITE
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