MAX34461EVKIT# Maxim Integrated, MAX34461EVKIT# Datasheet - Page 53

• Manufacturer Part Number: MAX34461EVKIT#
• Description: Power Management IC Development Tools MAX34461 Eval Kit
• Manufacturer: Maxim Integrated
• Type: Voltage Detectorsr

Specifications of MAX34461EVKIT#

• Rohs: yes
• Product: Evaluation Kits
• Tool Is For Evaluation Of: MAX34461
• Input Voltage: 3 V to 3.6 V
• Output Voltage: 3 V to 3.6 V
• Interface Type: USB
• Part # Aliases: 90-34461#EVK

The MFR_MARGIN_CONFIG command configures the
external DS4424 current DAC (if present) to margin the
associated power supplies. The MFR_MARGIN_CONFIG
command is described in
For the power supplies connected to PSENn (PAGES
0–15), power-supply margining is implemented using the
external DS4424 DAC outputs, according to
The device’s closed loop controls the DAC output current
setting to margin the power supply.
The device margins the power supplies when
OPERATION is set to one of the margin states. Margining
Table 30. MFR_MARGIN_CONFIG
Table 31. Power-Supply Margining with DS4424 DAC outputs
Maxim Integrated
PMBus 16-Channel Voltage Monitor and Sequencer
13:7
BIT
6:0
15
14
PAGE
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
OPEN_LOOP
DAC_VALUE
SLOPE
NAME
0
MFR_MARGIN_CONFIG (DFh)
Table
POWER SUPPLY
DAC setting to resulting voltage relationship.
0 = Negative slope (DAC source current results in a lower voltage).
1 = Positive slope (DAC source current results in a higher voltage).
0 = Normal closed-loop margining.
1 = DAC setting constantly to the DAC_VALUE when margining invoked.
These bits always return a 0.
When bit 14 is set, this 7-bit value is written to the external current DAC.
PSEN10
PSEN11
PSEN12
PSEN13
PSEN14
PSEN15
PSEN0
PSEN1
PSEN2
PSEN3
PSEN4
PSEN5
PSEN6
PSEN7
PSEN8
PSEN9
30.
Table
31.
DS4424 DEVICE
I
I
I
I
2
2
2
2
of the supplies does not begin until ALL power supplies
have exceeded their programmed POWER_GOOD_ON
levels. When this happens, the DAC output is enabled
and margining is initiated. The device then averages
four samples of V
measured V
MARGIN_HIGH or VOUT_MARGIN_LOW) differ by more
than 1%, the DAC setting is adjusted by one step that is
1/64 of full scale. The direction of the duty-cycle adjust-
ment is determined by the SLOPE bit in MFR_MARGIN_
CONFIG. All changes to the DAC setting are made after
averaging four samples of V
C address A0h
C address E0h
C address 20h
C address 60h
Unit 0
Unit 1
Unit 2
Unit 3
MEANING
OUT
and the target (set by either VOUT_
OUT
for a total time of 20ms. If the
OUT
DS4424 OUTPUT
MAX34461
over a 20ms period.
OUT0
OUT1
OUT2
OUT3
OUT0
OUT1
OUT2
OUT3
OUT0
OUT1
OUT2
OUT3
OUT0
OUT1
OUT2
OUT3
53