IS42S32200E-7BL-TR ISSI, Integrated Silicon Solution Inc, IS42S32200E-7BL-TR Datasheet - Page 32

• Manufacturer Part Number: IS42S32200E-7BL-TR
• Description: IC SDRAM 64MBIT 143MHZ 90BGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S32200E-7BL-TR

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (2Mx32)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-BGA
• Organization: 2Mx32
• Density: 64Mb
• Address Bus: 13b
• Access Time (max): 8/5.5ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 140mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS42S32200E, IS45S32200E
Fig CAP 3 - WRITE With Auto Precharge interrupted by a READ
Fig CAP 4 - WRITE With Auto Precharge interrupted by a WRITE
32
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto precharge):
A READ to bank m will interrupt a WRITE on bank n
when registered, with the data-out appearing CAS latency
later. The PRECHARGE to bank n will begin after t
is met, where t
registered.The last valid WRITE to bank n will be data-in
registered one clock prior to the READ to bank m.
Internal States
Internal States
COMMAND
COMMAND
ADDRESS
ADDRESS
BANK m
BANK m
BANK n
BANK n
CLK
CLK
DQ
DQ
wr
begins when the READ to bank m is
T0
Page Active
T0
Page Active
NOP
NOP
WRITE - AP
WRITE - AP
BANK n,
BANK n,
BANK n
BANK n
T1
T1
COL a
COL a
D
D
Page Active
IN
IN
WRITE with Burst of 4
a
a
Page Active
WRITE with Burst of 4
T2
D
T2
D
NOP
NOP
IN
IN
a+1
a+1
wr
READ - AP
BANK m,
BANK m
T3
T3
D
NOP
COL b
IN
Interrupt Burst, Write-Back
a+2
t
4.Interrupted by a WRITE (with or without auto precharge):
CAS Latency - 3 (BANK m)
WR
AWRITE to bank m will interrupt a WRITE on bank n when
registered.The PRECHARGE to bank n will begin after
t
m is registered. The last valid data WRITE to bank n
will be data registered one clock prior to a WRITE to
bank m.
- BANK n
wr
WRITE - AP
BANK m,
Integrated Silicon Solution, Inc. — www.issi.com
BANK m
T4
T4
NOP
COL b
D
is met, where t
Interrupt Burst, Write-Back
IN
READ with Burst of 4
b
t
WR
WRITE with Burst of 4
- BANK n
T5
T5
D
NOP
NOP
IN
b+1
wr
begins when the WRITE to bank
T6
T6
D
NOP
NOP
IN
D
Precharge
t
OUT
b+2
RP - BANK n
b
t
Precharge
RP - BANK n
DON'T CARE
DON'T CARE
T7
T7
D
NOP
D
NOP
Write-Back
IN
Precharge
OUT
b+3
t
t
RP - BANK m
RP - BANK m
b+1
07/12/2010
Rev. D