IS45S16400E-7TLA2-TR ISSI, Integrated Silicon Solution Inc, IS45S16400E-7TLA2-TR Datasheet - Page 34

• Manufacturer Part Number: IS45S16400E-7TLA2-TR
• Description: IC SDRAM 64MBIT 143MHZ 50TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS45S16400E-7TLA2-TR

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 50-TSOPII
• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 110mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Fig CAP 3 - WRITE With Auto Precharge interrupted by a READ
IS45S16400E
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto precharge):
Fig CAP 4 - WRITE With Auto Precharge interrupted by a WRITE
34
A READ to bank m will interrupt a WRITE on bank n
when registered, with the data-out appearing CAS latency
later. The PRECHARGE to bank n will begin after t
is met, where t
registered.The last valid WRITE to bank n will be data-in
registered one clock prior to the READ to bank m.
Internal States
COMMAND
Internal States
ADDRESS
COMMAND
ADDRESS
BANK m
BANK n
BANK m
BANK n
CLK
DQ
CLK
DQ
wr
begins when the READ to bank m is
Page Active
T0
NOP
T0
Page Active
NOP
WRITE - AP
BANK n,
BANK n
WRITE - AP
T1
COL a
BANK n,
D
Page Active
BANK n
T1
COL a
D
IN
WRITE with Burst of 4
IN
a
a
Page Active
WRITE with Burst of 4
D
T2
NOP
T2
D
IN
NOP
IN
a+1
a+1
READ - AP
wr
BANK m,
BANK m
T3
COL b
T3
D
NOP
Interrupt Burst, Write-Back
IN
a+2
t
CAS Latency - 3 (BANK m)
WR
4.Interrupted by a WRITE (with or without auto precharge):
- BANK n
AWRITE to bank m will interrupt a WRITE on bank n when
registered.The PRECHARGE to bank n will begin after
t
m is registered. The last valid data WRITE to bank n
will be data registered one clock prior to a WRITE to
bank m.
wr
WRITE - AP
T4
NOP
BANK m,
BANK m
Integrated Silicon Solution, Inc. — www.issi.com
T4
COL b
D
READ with Burst of 4
is met, where t
Interrupt Burst, Write-Back
IN
b
t
WR
WRITE with Burst of 4
- BANK n
T5
NOP
T5
D
NOP
IN
b+1
wr
begins when the WRITE to bank
T6
NOP
T6
D
NOP
D
Precharge
IN
t
OUT
RP - BANK n
b+2
b
t
Precharge
RP - BANK n
DON'T CARE
DON'T CARE
T7
NOP
D
T7
D
NOP
Precharge
OUT
Write-Back
IN
t
RP - BANK m
b+3
t
b+1
RP - BANK m
01/13/2010
Rev. F