IS42S16800E-6TL ISSI, Integrated Silicon Solution Inc, IS42S16800E-6TL Datasheet - Page 13

• Manufacturer Part Number: IS42S16800E-6TL
• Description: IC SDRAM 128MBIT 166MHZ 54TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS42S16800E-6TL

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS42S81600E, IS42S16800E
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
03/16/2011
CKE RELATED COMMAND TRUTH TABLE
Current State
Self-Refresh (S.R.)
Self-Refresh Recovery Idle After t
Power-Down (P.D.)
Both Banks Idle
Any state
other than
listed above
Notes:
1. H : High level, L : low level, X : High or low level (Don’t care).
2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup
before any command other than EXIT.
3. Power down and Self refresh can be entered only from the both banks idle state.
4. Must be legal command as defined in Operative Command Table.
5. Illegal if t
time must be satisfied
xsr
is not satisfied.
Operation
INVALID, CLK (n - 1) would exit S.R.
Self-Refresh Recovery
Self-Refresh Recovery
Illegal
Illegal
Maintain S.R.
Idle After t
Illegal
Illegal
Begin clock suspend next cycle
Begin clock suspend next cycle
Illegal
Illegal
Exit clock suspend next cycle
Maintain clock suspend
INVALID, CLK (n - 1) would exit P.D.
EXIT P.D. --> Idle
Maintain power down mode
Refer to operations in Operative Command Table H
Refer to operations in Operative Command Table H
Refer to operations in Operative Command Table H
Auto-Refresh
Refer to operations in Operative Command Table H
Refer to operations in Operative Command Table H
Refer to operations in Operative Command Table H
Refer to operations in Operative Command Table H
Self-Refresh
Refer to operations in Operative Command Table H
Power-Down
Refer to operations in Operative Command Table H
Begin clock suspend next cycle
Exit clock suspend next cycle
Maintain clock suspend
rc
rc
(3)
(3)
(2)
(2)
(2)
(2)
(5)
(5)
(4)
(1)
n-1
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
CKE
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
n
X
L
L
L
L
L
L
X
L
L
L
L
L
L
X
L
L
CS
X
H
X
H
H
X
X
X
X
X
H
H
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS
X
X
H
H
X
X
H
H
X
H
H
X
X
X
X
X
X
H
X
H
X
X
X
X
X
L
L
L
L
L
L
L
L
L
CAS
X
X
H
X
X
X
H
X
X
H
X
X
X
X
X
X
X
X
H
X
X
H
X
X
X
X
X
L
L
L
L
L
L
L
WE Address
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
Op - Code
Op - Code
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
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