MT46H16M16LFBF-6:A TR Micron Technology Inc, MT46H16M16LFBF-6:A TR Datasheet - Page 69

• Manufacturer Part Number: MT46H16M16LFBF-6:A TR
• Description: IC DDR SDRAM 256MBIT 60VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H16M16LFBF-6:A TR

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 256M (16Mx16)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 60-VFBGA
• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 6.5/5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 100mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1319-2

Figure 41:
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
Bank address
Command 1
(BA0, BA1)
Addresses
V
DQS
CK#
CKE
A10
DD
DM
V
DQ
CK
DD
Q
Initialize and Load Mode Registers
Notes:
LVCMOS
High level
T = 200µs
Power-up: V
NOP 2
1. PRE = PRECHARGE command; LMR = LOAD MODE REGISTER command; AR = AUTO REFRESH
2. NOP or DESELECT commands are required for at least 200µs.
3. Other valid commands are possible.
4. NOP or DESELECT commands are required during this time.
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DD
command; ACT = ACTIVE command; RA = row address; BA = bank address.
and CK stable
t IS
T0
NOP
High-Z
High-Z
t IH
t
CH
t
CK
t
CL
All banks
t IS
PRE
T1
t IH
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t RP 4
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Ta0
AR
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t RFC 4
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Load standard mode register
Tb0
AR
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x16, x32 Mobile DDR SDRAM
t RFC 4
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t IS
t IS
t IS
BA0 = L,
BA1 = L
CODE
CODE
Tc0
LMR
t IH
t IH
t IH
Load extended mode
t MRD 4
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register
BA0 = L,
BA1 = H
CODE
CODE
Td0
LMR
©2005 Micron Technology, Inc. All rights reserved.
t MRD 4
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Timing Diagrams
Te0
ACT
RA
RA
BA
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Don’t Care
Tf0
NOP 3