IS42S32400E-7TL ISSI, Integrated Silicon Solution Inc, IS42S32400E-7TL Datasheet - Page 17

• Manufacturer Part Number: IS42S32400E-7TL
• Description: IC SDRAM 128MBIT 143MHZ 86TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S32400E-7TL

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 128M (4Mx32)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 86-TSOPII
• Organization: 4Mx32
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 6.5/5.4ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 130mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 706-1066; IS42S32400E-7TL

IS42S32400E
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 00C
08/01/08
SYMBOL PARAMETER
—
—
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
cac
rcd
rac
rc
ras
rp
rrd
ccd
dpl
dal
rbd
wbd
rql
wdl
pql
qmd
dmd
mrd
Clock Cycle Time
Operating Frequency
CAS Latency
Active Command To Read/Write Command Delay Time
RAS Latency (t
Command Period (REF to REF / ACT to ACT)
Command Period (ACT to PRE)
Command Period (PRE to ACT)
Command Period (ACT[0] to ACT [1])
Column Command Delay Time
(READ, READA, WRIT, WRITA)
Input Data To Precharge Command Delay Time
Input Data To Active/Refresh Command Delay Time
(During Auto-Precharge)
Burst Stop Command To Output in HIGH-Z Delay Time
(Read)
Burst Stop Command To Input in Invalid Delay Time
(Write)
Precharge Command To Output in HIGH-Z Delay Time
(Read)
Precharge Command To Input in Invalid Delay Time
(Write)
Last Output To Auto-Precharge Start Time (Read)
DQM To Output Delay Time (Read)
DQM To Input Delay Time (Write)
Mode Register Set To Command Delay Time
rcd
+ t
cac
)
CAS Latency = 3
CAS Latency = 2
CAS Latency = 3
CAS Latency = 2
CAS Latency = 3
CAS Latency = 2
CAS Latency = 3
CAS Latency = 2
166
10
—
—
—
-2
—
6
3
3
6
7
3
2
1
2
5
3
0
3
0
2
0
2
143
10
–2
—
—
—
—
7
3
3
6
7
3
2
1
2
5
3
0
3
0
2
0
2
UNITS
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
MHz
ns
17