MT48LC4M32B2TG-7:G Micron Technology Inc, MT48LC4M32B2TG-7:G Datasheet - Page 32
![IC SDRAM 128MBIT 143MHZ 86TSOP](/photos/7/22/72264/557-86-tsop_sml.jpg)
MT48LC4M32B2TG-7:G
Manufacturer Part Number
MT48LC4M32B2TG-7:G
Description
IC SDRAM 128MBIT 143MHZ 86TSOP
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC4M32B2P-7G_TR.pdf
(67 pages)
Specifications of MT48LC4M32B2TG-7:G
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
128M (4Mx32)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
86-TSOPII
Organization
4Mx32
Density
128Mb
Address Bus
14b
Access Time (max)
17/8/5.5ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
175mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT48LC4M32B2TG-7:G
Manufacturer:
micron
Quantity:
415
Part Number:
MT48LC4M32B2TG-7:G
Manufacturer:
MICRONAS
Quantity:
20 000
Figure 23:
PRECHARGE
Power-Down
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. L 1/09 EN
PRECHARGE Command
A0-A9, A11
The PRECHARGE command (Figure 23) is used to deactivate the open row in a partic-
ular bank or the open row in all banks. The bank(s) will be available for a subsequent row
access some specified time (
determines whether one or all banks are to be precharged, and in the case where only
one bank is to be precharged, inputs BA0 and BA1 select the bank. When all banks are to
be precharged, inputs BA0 and BA1 are treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated prior to any READ or WRITE
commands being issued to that bank.
Power-down occurs if CKE is registered low coincident with a NOP or COMMAND
INHIBIT when no accesses are in progress (see Figure 24 on page 33). If power-down
occurs when all banks are idle, this mode is referred to as precharge power-down; if
power-down occurs when there is a row active in either bank, this mode is referred to as
active power-down. Entering power-down deactivates the input and output buffers,
excluding CKE, for maximum power savings while in standby. The device may not
remain in the power-down state longer than the refresh period (
refresh operations are performed in this mode.
The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE
HIGH at the desired clock edge (meeting
BA0,1
RAS#
CAS#
WE#
CKE
CLK
A10
CS#
HIGH
VALID ADDRESS
Bank Selected
All Banks
ADDRESS
BANK
t
RP) after the precharge command is issued. Input A10
32
DON’T CARE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
CKS).
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
Register Definition
t
REF or
t
REF
AT
) since no