IS42S32200E-7TLI ISSI, Integrated Silicon Solution Inc, IS42S32200E-7TLI Datasheet - Page 19

• Manufacturer Part Number: IS42S32200E-7TLI
• Description: IC SDRAM 64MBIT 143MHZ 86TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S32200E-7TLI

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (2Mx32)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 86-TSOPII
• Organization: 2Mx32
• Density: 64Mb
• Address Bus: 13b
• Access Time (max): 8/5.5ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 140mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 143 MHz
• Access Time: 5.5 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 140 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 706-1082; IS42S32200E-7TLI

IS42S32200E, IS45S32200E
CAS Latency
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
07/12/2010
same bank.The PRECHARGE command should be issued
x cycles before the clock edge at which the last desired
data element is valid, where x equals the CAS latency
minus one. This is shown in the READ to PRECHARGE
diagram for each possible CAS latency; data element n +
3 is either the last of a burst of four or the last desired of
a longer burst. Following the PRECHARGE command, a
subsequent command to the same bank cannot be issued
until t
hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the PRE-
rp
is met. Note that part of the row precharge time is
COMMAND
COMMAND
CLK
CLK
DQ
DQ
READ
READ
T0
T0
CAS Latency - 2
NOP
NOP
CAS Latency - 3
T1
T1
t
LZ
t
AC
CHARGE command is that it requires that the command
and address buses be available at the appropriate time to
issue the command; the advantage of the PRECHARGE
command is that it can be used to truncate fixed-length
or full-page bursts.
Full-page READ bursts can be truncated with the BURST
TERMINATE command, and fixed-length READ bursts
may be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated.The BURST
TERMINATE command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This is
shown in the READ Burst Termination diagram for each
possible CAS latency; data element n + 3 is the last desired
data element of a longer burst.
NOP
NOP
T2
T2
D
OUT
t
t
OH
LZ
t
AC
NOP
T3
T3
D
DON'T CARE
UNDEFINED
OUT
t
OH
T4
19