MT48LC32M8A2P-75 IT:D TR Micron Technology Inc, MT48LC32M8A2P-75 IT:D TR Datasheet - Page 64
![IC SDRAM 256MBIT 133MHZ 54TSOP](/photos/7/22/72261/557-54-tsop_sml.jpg)
MT48LC32M8A2P-75 IT:D TR
Manufacturer Part Number
MT48LC32M8A2P-75 IT:D TR
Description
IC SDRAM 256MBIT 133MHZ 54TSOP
Manufacturer
Micron Technology Inc
Datasheet
1.MT48LC16M16A2P-75D_TR.pdf
(92 pages)
Specifications of MT48LC32M8A2P-75 IT:D TR
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
256M (32M x 8)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
54-TSOP II
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 64 of 92
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Figure 34: WRITE-to-PRECHARGE
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Note:
Fixed-length WRITE bursts can be truncated with the BURST TERMINATE command.
When truncating a WRITE burst, the input data applied coincident with the BURST TER-
MINATE command is ignored. The last data written (provided that DQM is LOW at that
time) will be the input data applied one clock previous to the BURST TERMINATE com-
mand. This is shown in Figure 35 (page 65), where data n is the last desired data
element of a longer burst.
t
t
Command
Command
WR @
WR @
1. In this example DQM could remain LOW if the WRITE burst is a fixed length of two.
Address
Address
DQM
DQM
CLK
t
t
DQ
DQ
CK
CK < 15ns
15ns
WRITE
Bank a,
WRITE
Bank a,
Col n
D
Col n
D
T0
IN
IN
NOP
NOP
D
D
T1
IN
IN
t
WR
64
PRECHARGE
(a or all)
Bank
NOP
T2
t
WR
Micron Technology, Inc. reserves the right to change products or specifications without notice.
PRECHARGE
(a or all)
Bank
T3
NOP
t RP
NOP
NOP
T4
256Mb: x4, x8, x16 SDRAM
t RP
ACTIVE
Bank a,
NOP
Row
T5
© 1999 Micron Technology, Inc. All rights reserved.
WRITE Operation
Bank a,
Don’t Care
ACTIVE
NOP
Row
T6
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