MAX17059EVKIT# Maxim Integrated, MAX17059EVKIT# Datasheet - Page 14

• Manufacturer Part Number: MAX17059EVKIT#
• Description: Power Management IC Development Tools MAX17059 Eval Kit
• Manufacturer: Maxim Integrated
• Series: MAX17058, MAX17059r

Specifications of MAX17059EVKIT#

• Part # Aliases: 90-BCA1K#E00

Table 3. I
The ICs are compatible with any bus timing up to
400kHz. No special configuration is required to operate
at any speed.
The command protocols involve several transaction
formats. The simplest format consists of the master
writing the START bit, slave address, R/W bit, and then
monitoring the acknowledge bit for presence of the ICs.
More complex formats, such as the Write Data and Read
Data, read data and execute device-specific operations.
All bytes in each command format require the slave or
host to return an acknowledge bit before continuing with
the next byte.
transaction formats.
A write transaction transfers 2 or more data bytes to the
ICs. The data transfer begins at the memory address
supplied in the MAddr byte. Control of the SDA signal is
retained by the master throughout the transaction, except
for the acknowledge cycles:
A read transaction transfers 2 or more bytes from the
ICs. Read transactions are composed of two parts,
a write portion followed by a read portion, and are
therefore inherently longer than a write transaction. The
write portion communicates the starting point for the
Read: S. SAddr W. A. MAddr. A. Sr. SAddr R. A. Data0. A. Data1. N. P
Write: S. SAddr W. A. MAddr. A. Data0. A. Data1. A. P
MAddr
SAddr
KEY
Data
A
N
S
Write Portion
2
C Protocol Key
Table 3
START bit
Slave address (7 bit)
Memory address byte
Data byte written by master
Acknowledge bit—master
No acknowledge—master
Basic Transaction Formats
shows the key that applies to the
I
2
C Command Protocols
DESCRIPTION
Read Portion
Bus Timing
1-Cell /2-Cell Li+ ModelGauge ICs
read operation. The read portion follows immediately,
beginning with a Repeated START, slave address with
R/W set to a 1. Control of SDA is assumed by the ICs,
beginning with the slave address acknowledge cycle.
Control of the SDA signal is retained by the ICs through-
out the transaction, except for the acknowledge cycles.
The master indicates the end of a read transaction by
responding to the last byte it requires with a no acknowl-
edge. This signals the ICs that control of SDA is to remain
with the master following the acknowledge clock.
The write data protocol is used to write to register to the
ICs starting at memory address MAddr. Data0 represents
the data written to MAddr, Data1 represents the data
written to MAddr + 1, and DataN represents the last data
byte, written to MAddr + N. The master indicates the end
of a write transaction by sending a STOP or Repeated
START after receiving the last acknowledge bit:
The MSB of the data to be stored at address MAddr
can be written immediately after the MAddr byte is
acknowledged. Because the address is automatically
incremented after the LSB of each byte is received by
the ICs, the MSB of the data at address MAddr + 1 can
be written immediately after the acknowledgment of the
data at address MAddr. If the bus master continues an
autoincremented write transaction beyond address 4Fh,
the ICs ignore the data. A valid write must include both
register bytes. Data is also ignored on writes to read-
only addresses. Incomplete bytes and bytes that are not
acknowledged by the ICs are not written to memory.
S. SAddr W. A. MAddr. A. Data0. A. Data1. A... DataN. A. P
Data
KEY
Sr
W
N
P
A
MAX17058/MAX17059
Repeated START
R/W bit = 0
STOP bit
Data byte returned by slave
Acknowledge bit—slave
No acknowledge bit—slave
DESCRIPTION
Write Data Protocol
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