IS42S83200B-7TL ISSI, Integrated Silicon Solution Inc, IS42S83200B-7TL Datasheet - Page 45

• Manufacturer Part Number: IS42S83200B-7TL
• Description: IC SDRAM 256MBIT 143MHZ 54TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS42S83200B-7TL

• Package / Case: 54-TSOP II
• Memory Size: 256M (32M x 8)
• Format - Memory: RAM
• Memory Type: SDRAM
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Data Bus Width: 8 bit
• Organization: 32 Mbit x 8
• Maximum Clock Frequency: 143 MHz
• Access Time: 7 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 120 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 706-1027

IS42S83200B,
CLOCK SUSPEND
Clock suspend mode occurs when a column access/burst
is in progress and CKE is registered LOW. In the clock
suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled
LOW, the next internal positive clock edge is suspended.
Clock Suspend During WRITE Burst
Clock Suspend During READ Burst
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
07/28/08
INTERNAL
COMMAND
ADDRESS
CLOCK
COMMAND
INTERNAL
CKE
ADDRESS
CLK
DQ
CLOCK
CKE
CLK
DQ
IS42S16160B
READ
BANK a,
COL n
T0
NOP
T0
NOP
T1
WRITE
BANK a,
COL n
D
T1
IN
n
NOP
T2
D
OUT
T2
n
Any command or data present on the input pins at the time
of a suspended internal clock edge is ignored; any data
present on the DQ pins remains driven; and burst counters
are not incremented, as long as the clock is suspended.
(See following examples.)
Clock suspend mode is exited by registering CKE HIGH; the
internal clock and related operation will resume on the
subsequent positive clock edge.
T3
D
T3
OUT
n+1
NOP
T4
D
NOP
IN
T4
n+1
NOP
D
T5
OUT
D
DON'T CARE
n+2
NOP
IN
T5
n+2
DON'T CARE
NOP
D
T6
OUT
n+3
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