IS42S16800D-7B-TR ISSI, Integrated Silicon Solution Inc, IS42S16800D-7B-TR Datasheet - Page 24

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IS42S16800D-7B-TR

Manufacturer Part Number
IS42S16800D-7B-TR
Description
IC SDRAM 128MBIT 143MHZ 54BGA
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet

Specifications of IS42S16800D-7B-TR

Format - Memory
RAM
Memory Type
SDRAM
Memory Size
128M (8Mx16)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IS42S16800D-7B-TR
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
IS42S81600D,
REGISTER DEFINITION
Mode Register
The mode register is used to define the specific mode of
operation of the SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency, an
operating mode and a write burst mode, as shown in MODE
REGISTER DEFINITION.
The mode register is programmed via the LOAD MODE
REGISTER command and will retain the stored information
until it is programmed again or the device loses power.
MODE REGISTER DEFINITION
24
BA1 BA0 A11 A10
Reserved
IS42S16800D
Write Burst Mode
(1)
M9
0
1
A9
Mode
Programmed Burst Length
Single Location Access
Operating Mode
A8
M8 M7
— —
0
0
A7
Defined
M6-M0
Latency Mode
A6
M6 M5 M4
0
0
0
0
1
1
1
1
Mode
Standard Operation
All Other States Reserved
0
0
1
1
0
0
1
1
A5
0
1
0
1
0
1
0
1
Mode register bits M0-M2 specify the burst length, M3
specifies the type of burst (sequential or interleaved), M4- M6
specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifies the WRITE burst mode, and M10 and
M11 are reserved for future use.
The mode register must be loaded when all banks are idle,
and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
A4
Burst Type
Integrated Silicon Solution, Inc. — www.issi.com
CAS Latency
M3
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
A3
2
3
Interleaved
Sequential
1. To ensure compatibility with future devices,
A2
Burst Length
Type
should program BA1, BA0, A11, A10 = "0"
M2 M1 M0
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
A0
Reserved Reserved
Reserved Reserved
Reserved Reserved
Address Bus
Mode Register (Mx)
Full Page
M3=0
1
2
4
8
Reserved
M3=1
1
2
4
8
07/28/08
Rev. E

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