IS42S16160D-7TLI-TR ISSI, Integrated Silicon Solution Inc, IS42S16160D-7TLI-TR Datasheet - Page 47
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IS42S16160D-7TLI-TR
Manufacturer Part Number
IS42S16160D-7TLI-TR
Description
IC SDRAM 256MBIT 143MHZ 54TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Specifications of IS42S16160D-7TLI-TR
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
256M (16Mx16)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
54-TSOP II
Organization
16Mx16
Density
256Mb
Address Bus
15b
Access Time (max)
6.5/5.4ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
130mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
IS42S83200D, IS42S16160D
PRECHARGE
The PRECHARGE command (see figure) is used to deac-
tivate the open row in a particular bank or the open row in
all banks.The bank(s) will be available for a subsequent row
access some specified time (t
command is issued. Input A10 determines whether one or
all banks are to be precharged, and in the case where only
one bank is to be precharged, inputs BA0, BA1 select the
bank. When all banks are to be precharged, inputs BA0,
BA1 are treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to
that bank.
POWER-DOWN
Power-down occurs if CKE is registered LOW coincident
with a NOP or COMMAND INHIBIT when no accesses
are in progress. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down;
if power-down occurs when there is a row active in either
bank, this mode is referred to as active power-down.
Entering power-down deactivates the input and output
buffers, excluding CKE, for maximum power savings while
in standby. The device may not remain in the power-down
state longer than the refresh period (64ms) since no refresh
operations are performed in this mode.
The power-down state is exited by registering a NOP or
COMMAND INHIBIT and CKE HIGH at the desired clock
edge (meeting t
POWER-DOWN
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00D
12/12/07
cks
COMMAND
). See figure below.
CKE
CLK
All banks idle
Enter power-down mode
rp
) after the PRECHARGE
t
NOP
CKS
Input buffers gated off
less than 64ms
PRECHARGE Command
Exit power-down mode
A0-A9, A11, A12
BA0, BA1
CKE
RAS
CAS
CLK
A10
WE
≥ t
CS
CKS
NOP
HIGH
DON'T CARE
ACTIVE
BANK ADDRESS
BANK SELECT
ALL BANKS
t
t
t
RCD
RAS
RC
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