IS42S16160D-6TLI ISSI, Integrated Silicon Solution Inc, IS42S16160D-6TLI Datasheet - Page 50
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IS42S16160D-6TLI
Manufacturer Part Number
IS42S16160D-6TLI
Description
IC SDRAM 256MBIT 166MHZ 54TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Specifications of IS42S16160D-6TLI
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
256M (16Mx16)
Speed
166MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
54-TSOP II
Organization
16Mx16
Density
256Mb
Address Bus
15b
Access Time (max)
6.5/5.4ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
180mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
WRITE With Auto Precharge interrupted by a WRITE
IS42S83200D, IS42S16160D
WRITE With Auto Precharge interrupted by a READ
50
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto precharge):
A READ to bank m will interrupt a WRITE on bank n when
registered, with the data-out appearing (CAS latency)
later. The PRECHARGE to bank n will begin after t
is met, where t
registered.The last valid WRITE to bank n will be data-in
registered one clock prior to the READ to bank m.
Internal States
Internal States
COMMAND
COMMAND
ADDRESS
ADDRESS
BANK m
BANK m
BANK n
BANK n
CLK
CLK
DQ
DQ
dpl
begins when the READ to bank m is
Page Active
Page Active
T0
T0
NOP
NOP
WRITE - AP
WRITE - AP
BANK n,
BANK n,
T1
BANK n
T1
BANK n
COL a
COL a
D
D
Page Active
IN
IN
WRITE with Burst of 4
a
a
Page Active
WRITE with Burst of 4
T2
D
T2
D
NOP
NOP
IN
IN
a+1
a+1
dpl
READ - AP
BANK m,
BANK m
T3
T3
D
NOP
COL b
IN
Interrupt Burst, Write-Back
a+2
4.Interrupted by a WRITE (with or without auto precharge):
t
CAS Latency - 3 (BANK m)
DPL
AWRITE to bank m will interrupt a WRITE on bank n when
registered.The PRECHARGE to bank n will begin after
t
m is registered. The last valid data WRITE to bank n
will be data registered one clock prior to a WRITE to
bank m.
dpl
- BANK n
Integrated Silicon Solution, Inc. — www.issi.com
WRITE - AP
BANK m,
BANK m
T4
T4
NOP
COL b
D
is met, where t
Interrupt Burst, Write-Back
IN
READ with Burst of 4
b
t
DPL
WRITE with Burst of 4
- BANK n
T5
T5
D
NOP
NOP
IN
b+1
dpl
begins when the WRITE to bank
T6
T6
D
NOP
NOP
IN
D
Precharge
t
OUT
b+2
RP - BANK n
b
t
Precharge
RP - BANK n
DON'T CARE
DON'T CARE
T7
T7
D
NOP
NOP
D
Write-Back
IN
Precharge
OUT
b+3
t
t
RP - BANK m
DPL - BANK m
b+1
Rev. 00D
12/12/07