IS61LV12824-10TQ ISSI, Integrated Silicon Solution Inc, IS61LV12824-10TQ Datasheet

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IS61LV12824-10TQ

Manufacturer Part Number
IS61LV12824-10TQ
Description
IC SRAM 3MBIT 10NS 100TQFP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet

Specifications of IS61LV12824-10TQ

Format - Memory
RAM
Memory Type
SRAM - Asynchronous
Memory Size
3M (128K x 24)
Speed
10ns
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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FUNCTIONAL BLOCK DIAGRAM
IS61LV12824
128K x 24 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY
FEATURES
• High-speed access time: 8, 10 ns
• CMOS low power operation
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
• Three state outputs
• Available in 119-pin Plastic Ball Grid Array
• Industrial temperature available
• Lead-free available
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
06/22/05
— 756 mW (max.) operating @ 8 ns
— 36 mW (max.) standby @ 8 ns
required
(PBGA) and 100-pin TQFP packages.
I/O0-I/O23
A0-A16
VCC
GND
CE2
CE1
CE2
OE
WE
DECODER
CIRCUIT
CONTROL
CIRCUIT
DATA
I/O
DESCRIPTION
The
as 131,072 words by 24 bits. It is fabricated using
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields ac-
cess times as fast as 8 ns with low power consumption.
When CE1, CE2 are HIGH and CE2 is LOW (deselected), the
device assumes a standby mode at which the power dissipa-
tion can be reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE1, CE2, CE2 and OE. The active
LOW Write Enable (WE) controls both writing and reading of
the memory.
The IS61LV12824 is packaged in the JEDEC standard
119-pin PBGA and 100-pin TQFP.
ISSI
IS61LV12824 is a high-speed, static RAM organized
MEMORY ARRAY
COLUMN I/O
128K x 24
ISSI
JUNE 2005
ISSI
's high-
®
1

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IS61LV12824-10TQ Summary of contents

Page 1

... Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE1, CE2, CE2 and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61LV12824 is packaged in the JEDEC standard 119-pin PBGA and 100-pin TQFP. DECODER MEMORY ARRAY ...

Page 2

... IS61LV12824 PIN CONFIGURATION - 119-pin PBGA A11 A14 A15 CE1 B NC A12 A13 C I/O16 NC CE2 NC D I/O17 V GND GND CCQ E I/O18 GND V GND CC F I/O19 V GND GND CCQ G I/O20 GND V GND CC H I/O21 V GND GND CCQ J V GND V GND CCQ CC K I/O22 ...

Page 3

... IS61LV12824 PIN CONFIGURATION 100-Pin TQFP 100 Vcc GND 3 4 I/O16 5 I/O17 6 GND Vcc I/O18 9 I/O19 10 GND 11 Vcc Q 12 I/O20 13 I/O21 14 Vcc GND 18 I/O22 19 I/O23 20 Vcc Q 21 GND 22 I/O12 23 I/O13 24 Vcc Q 25 GND 26 I/O14 27 I/O15 28 Vcc 29 GND PIN DESCRIPTIONS A0-A16 Address Inputs ...

Page 4

... IS61LV12824 TRUTH TABLE Mode Not Selected Output Disabled H Read H Write L ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Power Supply Voltage Relative to GND CC V Terminal Voltage with Respect to GND TERM T Storage Temperature STG T Temperature Under Bias: BIAS P Power Dissipation Output Current OUT Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...

Page 5

... IS61LV12824 POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions I Vcc Dynamic Operating Supply Current I OUT I TTL Standby Current (TTL Inputs CE1, CE2 CMOS Standby CE1, CE2 Current (CMOS Inputs) CE2 0.2V Note address and data inputs are cycling at the maximum frequency means no input lines change. ...

Page 6

... IS61LV12824 READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Read Cycle Time RC t Address Access Time AA t Output Hold Time OHA CE1, CE2 Access Time t ACE t CE2 Access Time 2 ACE OE Access Time t DOE OE to High-Z Output t (2) HZOE OE to Low-Z Output t (2) LZOE ...

Page 7

... IS61LV12824 AC WAVEFORMS (1,2) (Address Controlled) (CE1 = CE2 = READ CYCLE NO. 1 ADDRESS D OUT PREVIOUS DATA VALID (1,3) READ CYCLE NO. 2 ADDRESS OE CS1 CS2 t LZCS1 t LZCS2 HIGH-Z D OUT Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1, CE2 = V 3. Address is valid prior to or coincident with CE1, CE2 LOW and CE2 HIGH transition. ...

Page 8

... IS61LV12824 WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Write Cycle Time WC CE1, CE2 to Write End t SCE t CE2 to Write End 2 SCE t Address Setup Time AW to Write End t Address Hold from Write End HA t Address Setup Time SA WE Pulse Width (OE = HIGH PWE WE Pulse Width (OE = LOW) ...

Page 9

... IS61LV12824 (CE Controlled HIGH or LOW) WRITE CYCLE NO. 1 ADDRESS t SA CE1 CE2 WE D DATA UNDEFINED OUT D IN (1) (WE Controlled HIGH during Write Cycle) WRITE CYCLE NO. 2 ADDRESS OE CE1 LOW HIGH CE2 DATA UNDEFINED OUT D IN Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. D ...

Page 10

... IS61LV12824 WRITE CYCLE NO. 3 (1) (WE Controlled: OE ADDRESS OE LOW CE1 LOW HIGH CE2 DATA UNDEFINED OUT D IN Note: 1. The internal Write time is defined by the overlap of CE1 and CE2 = LOW, CE2 = HIGH and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that terminates the Write ...

Page 11

... IS61LV12824-10TQ Industrial Range: –40°C to +85°C Speed (ns) Order Part No. 8 IS61LV12824-8BI 10 IS61LV12824-10BI IS61LV12824-10TQI IS61LV12824-10TQLI Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. D 06/22/05 Package Plastic Ball Grid Array Plastic Ball Grid Array, Lead-free TQFP Plastic Ball Grid Array Plastic Ball Grid Array, Lead-free ...

Page 12

PACKAGING INFORMATION Plastic Ball Grid Array Package Code: B (119-pin MILLIMETERS Sym. Min. Max. N0. Leads 119 A — 2.41 A1 0.50 0.70 A2 0.80 1.00 A3 1.30 1.70 A4 0.56 BSC b 0.60 0.90 D 21.80 ...

Page 13

PACKAGING INFORMATION TQFP (Thin Quad Flat Pack Package) Package Code Thin Quad Flat Pack (TQ) Millimeters Inches Symbol Min Max Min Ref. Std. No. Leads (N) 100 A — 1.60 — A1 0.05 0.15 ...

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