IS61LPS12836A-200B2I ISSI, Integrated Silicon Solution Inc, IS61LPS12836A-200B2I Datasheet - Page 10

• Manufacturer Part Number: IS61LPS12836A-200B2I
• Description: IC SRAM 4MBIT 200MHZ 119BGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS61LPS12836A-200B2I

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 4M (128K x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 119-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
TRUTH TABLE
NOTE:
10
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (BWa-d) and BWE are LOW or GW is LOW. WRITE = H for all
3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write
OPERATION
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Snooze Mode, Power-Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
PARTIAL TRUTH TABLE
Function
Read
Read
Write Byte 1
Write All Bytes
Write All Bytes
BWx, BWE, GW HIGH.
DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are available on the x18 version. DQPa-DQPd are
available on the x36 version.
input data hold time.
enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
(1-8)
GW
GW
GW
GW
GW
H
H
H
H
L
ADDRESS CE
External
External
External
External
External
Current
Current
Current
Current
Current
Current
None
None
None
None
None
None
Next
Next
Next
Next
Next
Next
BWE
BWE
BWE
BWE
BWE
H
X
L
L
L
CE
CE
CE
CE
H
H
H
H
H
H
H
L
L
L
L
X
L
L
L
L
L
X
X
X
X
X
X
BWa
BWa
BWa
BWa
BWa
CE2
CE2
CE2
CE2
CE2
X
H
X
L
L
H
H
X
X
X
X
X
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
CE2
BWb
BWb
BWb
BWb
BWb
X
X
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
X
H
H
X
L
ZZ
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
BWc
BWc
BWc
BWc
BWc
ADSP
ADSP
ADSP
ADSP
ADSP
X
H
H
X
L
H
H
H
H
H
H
H
H
H
X
H
H
X
X
X
X
X
X
X
L
L
L
L
BWd
BWd
BWd
BWd
BWd
ADSC
ADSC
ADSC
ADSC
ADSC ADV
X
H
H
X
L
H
H
H
H
H
H
H
H
H
H
H
H
L
X
X
L
L
X
X
X
L
L
L
ADV
ADV
ADV
ADV
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
Integrated Silicon Solution, Inc.
WRITE
WRITE
WRITE
WRITE
WRITE OE
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
OE
OE
OE
OE
H
H
H
H
H
H
X
X
X
X
X
X
L
X
L
L
L
X
X
L
L
X
X
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
X
01/07/2010
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DQ
Q
D
Q
Q
Q
D
D
Q
Q
D
D
Rev. H