IS42S16320B-7TL ISSI, Integrated Silicon Solution Inc, IS42S16320B-7TL Datasheet - Page 6

• Manufacturer Part Number: IS42S16320B-7TL
• Description: IC SDRAM 512MBIT 143MHZ 54TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS42S16320B-7TL

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN FUNCTIONS
DQ
DQ
IS42S86400B, IS42/45S16320B
6
BA0, BA1
0
0
Symbol
A0-A12
DQML,
-DQ
DQMH
-DQ
DQM
V
V
CAS
CKE
RAS
CLK
V
WE
V
CS
ddq
ssq
dd
ss
7
15
(x8) or
(x16)
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input/Output
Input Pin
Input Pin
P ower Supply Pin
P ower Supply Pin
P ower Supply Pin
P ower Supply Pin
Type
Function (In Detail)
Address Inputs: A0-A12 are sampled during the ACTIVE command (row-address
A0-A12) and READ/WRITE command (column address A0-A9 (x16); A0-A9, A11
(x8); with A10 defining auto precharge) to select one location out of the memory
array in the respective bank. A10 is sampled during a PRECHARGE command to
determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0,
BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE
REGISTER command.
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE
or PRECHARGE command is being applied.
CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" for details on device commands.
The CKE input determines whether the CLK input is enabled. The next rising edge
of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE
is LOW, the device will be in either power-down mode, clock suspend mode, or self
refresh mode. CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH.
DQML and DQMH control the lower and upper bytes of the I/O buffers. In read
mode,DQML and DQMH control the output buffer. WhenDQML orDQMH is LOW, the
corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to
the HIGH impedance state whenDQML/DQMH is HIGH. This function corresponds to
OE in conventional DRAMs. In write mode,DQML and DQMH control the input buffer.
When DQML or DQMH is LOW, the corresponding buffer byte is enabled, and data
can be written to the device. WhenDQML or DQMH is HIGH, input data is masked
and cannot be written to the device. For IS42/45S16320B only.
For IS42S86400B only.
Data on the Data Bus is latched on DQ pins during Write commands, and buffered for
output after Read commands.
RAS, in conjunction with CAS and WE, forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
WE, in conjunction with RAS and CAS, forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
V
V
V
V
ddq
dd
ssq
ss
is the device internal ground.
is the device internal power supply.
is the output buffer ground.
is the output buffer power supply.
Integrated Silicon Solution, Inc. — www.issi.com
04/08/2011
Rev. G