IS61LF51236A-7.5TQI ISSI, Integrated Silicon Solution Inc, IS61LF51236A-7.5TQI Datasheet - Page 7
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IS61LF51236A-7.5TQI
Manufacturer Part Number
IS61LF51236A-7.5TQI
Description
IC SRAM 18MBIT 7.5NS 100TQFP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet
1.IS61LF51236A-7.5TQLI-TR.pdf
(35 pages)
Specifications of IS61LF51236A-7.5TQI
Format - Memory
RAM
Memory Type
SRAM - Synchronous
Memory Size
18M (512K x 36)
Speed
7.5ns
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS61LF51236A-7.5TQI
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
Company:
Part Number:
IS61LF51236A-7.5TQI-TR
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
PIN DESCRIPTIONS
IS61LF25672A
IS61VF25672A
Integrated Silicon Solution, Inc.
Rev. K
07/29/2010
165 PBGA PACKAGE PIN CONFIGURATION
512K
Note: * A
Symbol
A
A0, A1
ADV
ADSP
ADSC
GW
CLK
CE, CE2, CE2
BWx (x=a,b,c,d) Synchronous Byte Write
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
X
1
NC
NC
DQPc
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
DQPd
NC
MODE
36 (TOP VIEW)
0
and A
1
are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
2
A
A
NC
DQc
DQc
DQc
DQc
Vss
DQd
DQd
DQd
DQd
NC
NC
NC
Pin Name
Address Inputs
Synchronous Burst Address
Inputs
Synchronous Burst Address
Advance.
Address Status Processor
Address Status Controller
Global Write Enable
Synchronous Clock
Synchronous Chip Select
Controls
IS61LF51236A
IS61VF51236A IS61VF102418A
3
CE
CE2
V
V
V
V
V
NC
V
V
V
V
V
A
A
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
4
BWc
BWd
Vss
V
V
V
V
V
V
V
V
V
Vss
A
A
DD
DD
DD
DD
DD
DD
DD
DD
DD
5
BWb
BWa
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
TDI
TMS
IS61LF102418A
6
CE2
CLK
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
A
A
A
1
0
*
*
Symbol
BWE
OE
ZZ
MODE
TCK, TDO
TMS, TDI
NC
DQa-DQd
DQPa-Pd
V
V
Vss
DD
DDQ
7
BWE
GW
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
TDO
TCK
8
ADSC
OE
Vss
V
V
V
V
V
V
V
V
V
Vss
A
A
DD
DD
DD
DD
DD
DD
DD
DD
DD
Burst Sequence Selection
JTAG Pins
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Pin Name
Byte Write Enable
Output Enable
Power Sleep Mode
Power Supply
Output Power Supply
Ground
9
ADV
ADSP
V
V
V
V
V
NC
V
V
V
V
V
A
A
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
10
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
DQPb
DQPa
11
NC
NC
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
A
A
7