IS61LPD51236A-200TQI ISSI, Integrated Silicon Solution Inc, IS61LPD51236A-200TQI Datasheet
IS61LPD51236A-200TQI
Specifications of IS61LPD51236A-200TQI
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IS61LPD51236A-200TQI Summary of contents
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... IS61VPD51236a IS61VPD102418a IS61lPD51236a IS61lPD102418a 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPElINED, DOUBlE CYClE DESElECT STaTIC RaM FEaTURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • ...
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... IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A BLOCK DIAGRAM CLK ADV ADSC ADSP 19/ BWE BWd (x36) BWc (x36) BWb (x36/x18) BWa (x36/x18) CE CE2 CE2 OE 2 MODE A0' Q0 CLK A0 BINARY COUNTER A1 CLR MEMORY ARRAY 17/18 19/ ADDRESS REGISTER CE CLK 36 DQd BYTE WRITE REGISTERS CLK D Q DQc ...
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... IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A 165-PIN BGa 165-Ball, 13x15 mm BGA 1mm Ball Pitch, 11x15 Ball Array BOTTOM VIEW Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 07/08/08 3 ...
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... IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A 165 PBGA PACKAGE PIN CONFIGURATION 512k 36 (TOP VIEW CE2 C DQPc NC V ddq D DQc DQc V ddq E DQc DQc V ddq F DQc DQc V ddq G DQc DQc V ddq H NC Vss NC J DQd DQd V ddq K DQd DQd V ddq l DQd DQd V ddq M DQd ...
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... IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A 165 PBGA PACKAGE PIN CONFIGURATION 1M 18 (TOP VIEW CE2 ddq D NC DQb V ddq E NC DQb V ddq F NC DQb V ddq G NC DQb V ddq H NC Vss NC J DQb NC V ddq K DQb NC V ddq l DQb NC V ddq M DQb NC V ddq ...
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... IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A PIN CONFIGURATION 100-PIN TQFP 100 DQPc 1 2 DQc DQc 3 4 VDDQ 5 VSS DQc 6 7 DQc 8 DQc 9 DQc VSS 10 11 VDDQ 12 DQc DQc VDD 16 NC VSS 17 18 DQd 19 DQd VDDQ 20 VSS 21 22 DQd 23 DQd DQd 24 25 DQd 26 VSS ...
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... IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A PIN CONFIGURATION 100-PIN TQFP 100 VDDQ 4 VSS DQb DQb 9 10 VSS 11 VDDQ 12 DQb DQb VDD VSS DQb 18 DQb 19 20 VDDQ 21 VSS 22 DQb DQb 23 DQPb VSS 27 VDDQ 1024K x 18 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus ...
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... IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A TRUTH TaBlE (3CE option) (1-8) OPERaTION aDDRESS Deselect Cycle, Power-Down None Deselect Cycle, Power-Down None Deselect Cycle, Power-Down None Deselect Cycle, Power-Down None Deselect Cycle, Power-Down None Snooze Mode, Power-Down None Read Cycle, Begin Burst External Read Cycle, Begin Burst ...
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... IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A TRUTH TaBlE (1CE option) (1-8) NEXT CYClE Deselected Read, Begin Burst Read, Begin Burst Write, Begin Burst Read, Begin Burst Read, Begin Burst Read, Continue Burst Read, Continue Burst Read, Continue Burst Read, Continue Burst Write, Continue Burst ...
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... IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A INTERlEaVED BURST aDDRESS TaBlE (MODE = V External address 1st Burst address lINEaR BURST aDDRESS TaBlE (MODE = VSS) A1', A0' = 1,1 aBSOlUTE MaXIMUM RaTINGS Symbol Parameter T Storage Temperature sTg P Power Dissipation d I Output Current (per I/O) OuT Voltage Relative to Vss for I/O Pins ...
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... IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A OPERaTING RaNGE (IS61lPDXXXXX) Range ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C OPERaTING RaNGE (IS61VPDXXXXX) Range ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C DC ElECTRICal CHaRaCTERISTICS Symbol Parameter V Output HIGH Voltage ...
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... IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A CaPaCITaNCE (1,2) Symbol Parameter c Input Capacitance IN c Input/Output Capacitance OuT Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions 25° MHz 3.3V I/O aC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times ...
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... IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A 2.5V I/O aC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load 2.5 I/O OUTPUT lOaD EQUIValENT Z = 50Ω O Output Buffer Figure 3 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev ...
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... IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A REaD/WRITE CYClE SWITCHING CHaRaCTERISTICS Symbol Parameter f Clock Frequency MAx t Cycle Time kc t Clock High Time kh t Clock Low Time kl t Clock Access Time kq t Clock High to Output Invalid (2) kqx t Clock High to Output Low-Z (2,3) kqlZ t Clock High to Output High-Z ...
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... IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A REaD/WRITE CYClE TIMING t KC CLK ADSP t SS ADSC ADV Address RD1 BWE BWx t t CES CEH CES CEH CE2 t t CES CEH CE2 t OEQ OE t OELZ High-Z DATA OUT t KQLZ t KQ High-Z DATA IN Single Read Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev ...
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... IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A WRITE CYClE TIMING t KC CLK ADSP ADSC ADV must be inactive for ADSP Write ADV Address WR1 BWE WR1 BWx t t CES CEH CES CEH CE2 t t CES CEH CE2 OE High-Z DATA OUT t DS High-Z DATA 1a IN Single Write ...
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... IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A SNOOZE MODE ElECTRICal CHaRaCTERISTICS Symbol Parameter I Current during SNOOZE MODE active to input ignored Pds t ZZ inactive to input sampled Pus t ZZ active to SNOOZE current ZZI t ZZ inactive to exit SNOOZE current rZZI SNOOZE MODE TIMING CLK t PDS ZZ setup cycle ...
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... IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A IEEE 1149.1 SERIal BOUNDaRY SCaN (JTaG) The IS61LPD/VPD51236A and IS61LPD/VPD102418A have a serial boundary scan Test Access Port (TAP) in the PBGA package only. (The TQFP package not available.) This port operates in accordance with IEEE Standard 1149.1-1900, but does not include all functions required for full 1149 ...
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... IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A TEST DaTa OUT (TDO) The TDO output pin is used to serially clock data-out from the registers.The output is active depending on the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK and TDO is connected to the Least Significant Bit (LSB) of any register ...
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... IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A TaP INSTRUCTION SET Eight instructions are possible with the three-bit instruction register and all combinations are listed in the Instruction Code table. Three instructions are listed as RESERVED and should not be used and the other five instructions are described below. The TAP controller used in this SRAM is not fully compliant with the 1149 ...
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... IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A INSTRUCTION CODES Code Instruction Description 000 EXTEST Captures the Input/Output ring contents. Places the boundary scan register be- tween the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant. 001 IDCODE Loads the ID register with the vendor ID code and places the register between TDI and TDO ...
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... IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A TaP Electrical Characteristics Over the Operating Range Symbol Parameter V Output HIGH Voltage Oh1 V Output HIGH Voltage Oh2 V Output LOW Voltage Ol1 V Output LOW Voltage Ol2 V Input HIGH Voltage Ih V Input LOW Voltage Il I Input Load Current x Notes: 1. All Voltage referenced to Ground. (AC) ≤ ...
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... IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A TaP aC TEST CONDITIONS (2.5/3.3V) Input pulse levels 0 to 2.5V/0 to 3.0V Input rise and fall times Input timing reference levels Output reference levels Test load termination supply voltage TaP TIMING 1 t THTH TCK TMS TDI TDO Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev ...
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... IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A 165 PBGa BOUNDaRY SCaN ORDER (x 36) Signal Bump Bit # Name ID Bit # 1 MODE 11P 10P 10R 11R 11H 31 12 DQa 11N 32 13 DQa 11M 33 14 DQa 11L 34 15 DQa 11K 35 16 DQa 11J 36 17 DQa 10M 37 18 DQa ...
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... IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A 165 PBGa BOUNDaRY SCaN ORDER (x 18) Signal Bump Bit # Name ID Bit # 1 MODE 11P 10P 10R 11R 11H 11N 11M 11L 11K 11J 36 17 DQa 10M 37 18 DQa 10L 38 19 DQa 10K 39 20 DQa 10J 40 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev ...
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... Order Part Number IS61LPD51236A-250TQ IS61LPD51236A-250B3 IS61LPD51236A-200TQ IS61LPD51236A-200B3 IS61LPD102418A-250TQ IS61LPD102418A-250B3 IS61LPD102418A-200TQ IS61LPD102418A-200B3 Order Part Number IS61LPD51236A-250TQI IS61LPD51236A-250B3I IS61LPD51236A-250B3LI IS61LPD51236A-200TQI IS61LPD51236A-200TQLI IS61LPD51236A-200B3I IS61LPD102418A-250TQI IS61LPD102418A-250B3I IS61LPD102418A-200TQI IS61LPD102418A-200B3I Integrated Silicon Solution, Inc. — 1-800-379-4774 Package 100 TQFP 165 PBGA 100 TQFP 165 PBGA 100 TQFP ...
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... IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A ORDERING INFORMaTION (2.5V core/2.5V I/O) Commercial Range: 0°C to +70°C Configuration Frequency 512Kx36 250 200 1Mx18 250 200 Industrial Range: -40°C to +85°C Configuration Frequency 512Kx36 250 200 1Mx18 250 200 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev ...
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PACKAGING INFORMATION TQFP (Thin Quad Flat Pack Package) Package Code Thin Quad Flat Pack (TQ) Millimeters Inches Symbol Min Max Min Ref. Std. No. Leads (N) 100 A — 1.60 — A1 0.05 0.15 ...
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PACKAGING INFORMATION Ball Grid Array Package Code: B (165-pin) TOP VIEW A1 CORNER BGA - 13mm ...