IS61WV102416BLL-10MLI ISSI, Integrated Silicon Solution Inc, IS61WV102416BLL-10MLI Datasheet - Page 12

IC SRAM 16MBIT 10NS 48MBGA

IS61WV102416BLL-10MLI

Manufacturer Part Number
IS61WV102416BLL-10MLI
Description
IC SRAM 16MBIT 10NS 48MBGA
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet

Specifications of IS61WV102416BLL-10MLI

Format - Memory
RAM
Memory Type
SRAM - Asynchronous
Memory Size
16M (1M x 16)
Speed
10ns
Interface
Parallel
Voltage - Supply
2.4 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
48-MBGA
Density
16Mb
Access Time (max)
10ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
3.3V
Address Bus
20b
Package Type
TFBGA
Operating Temp Range
-40C to 85C
Number Of Ports
1
Supply Current
95mA
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.465V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Word Size
16b
Number Of Words
1M
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
706-1054
IS61WV102416BLL-10MLI

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IS61WV102416BLL-10MLI
Manufacturer:
ISSI
Quantity:
4
Part Number:
IS61WV102416BLL-10MLI
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
Part Number:
IS61WV102416BLL-10MLI-TR
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
IS61WV102416ALL
IS61WV102416BLL
IS64WV102416BLL
WRITE CYCLE SWITCHING CHARACTERISTICS
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any
12
Symbol
Notes:
specified in Figure 1.
one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that
terminates the write. Shaded area product in development
t
t
t
t
t
t
t
t
t
t
t
t
WC
HD
SCE
AW
HA
SA
PWB
PWE
PWE
SD
HZWE
LZWE
1
2
(2)
(2)
Parameter
Write Cycle Time
CE to Write End
Address Setup Time
to Write End
Address Hold from Write End
Address Setup Time
LB, UB Valid to End of Write
WE Pulse Width
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
Integrated Silicon Solution, Inc. — www.issi.com —
Min.
6.5
6.5
6.5
6.5
8.0
8
0
0
5
0
2
-8
Max.
3.5
(1,3)
(Over Operating Range)
Min.
10
10
8
8
0
0
8
8
6
0
2
-10
Max.
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1-800-379-4774
06/05/09
Rev. E

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