MT46V64M16TG-6T IT:A TR Micron Technology Inc, MT46V64M16TG-6T IT:A TR Datasheet - Page 56
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MT46V64M16TG-6T IT:A TR
Manufacturer Part Number
MT46V64M16TG-6T IT:A TR
Description
IC DDR SDRAM 1GBIT 6NS 66TSOP
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46V256M4P-6TA_TR.pdf
(82 pages)
Specifications of MT46V64M16TG-6T IT:A TR
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
1G (64M x 16)
Speed
6ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
-40°C ~ 85°C
Package / Case
66-TSOP
Organization
64Mx16
Density
1Gb
Address Bus
16b
Access Time (max)
700ps
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Package Type
TSOP
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
275mA
Pin Count
66
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 28:
PDF: 09005aef80a2f898/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
Random READ Accesses
Notes:
Command
Command
Command
Address
Address
Address
DQS
DQS
DQS
CK#
CK#
CK#
DQ
DQ
DQ
CK
CK
CK
1. DO n (or x or b or g) = data-out from column n (or column x or column b or column g).
2. BL = 2, BL = 4, or BL = 8 (if BL = 4 or BL = 8, the following burst interrupts the previous).
3. n', x', b', or g' indicate the next data-out following DO n, DO x, DO b, or DO g, respectively.
4. READs are to an active row in any bank.
5. Shown with nominal
Bank,
READ
Col n
READ
Bank,
READ
Bank,
Col n
Col n
T0
T0
T0
CL = 2
Bank,
Col x
Bank,
READ
READ
READ
Bank,
Col x
Col x
T1
T1
T1
CL = 2.5
t
AC,
CL = 3
t
T2
DQSCK, and
56
Bank,
Col b
READ
READ
READ
Bank,
Bank,
Col b
Col b
T2n
T2
T2
DO
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
T2n
DQSQ.
T3
DO
DO
n'
n
Bank,
Col g
Bank,
Col g
T3n
READ
READ
Bank,
READ
Col g
T3
T3
DO
DO
DO
1Gb: x4, x8, x16 DDR SDRAM
n'
n
x
T3n
T3n
T4
Transitioning Data
DO
DO
n'
DO
x'
x
T4n
T4
T4
NOP
NOP
NOP
©2003 Micron Technology, Inc. All rights reserved.
DO
DO
DO
x
x'
b
T4n
T4n
T5
DO
DO
x'
DO
b'
b
T5n
T5
T5
NOP
NOP
NOP
Operations
DO
Don’t Care
DO
DO
b'
b
g
T5n
T5n
DO
b'