M25P40-VMP6TG NUMONYX, M25P40-VMP6TG Datasheet - Page 27
![IC FLASH 4MBIT 50MHZ 8VFQFPN](/photos/18/97/189768/3778330_sml.jpg)
M25P40-VMP6TG
Manufacturer Part Number
M25P40-VMP6TG
Description
IC FLASH 4MBIT 50MHZ 8VFQFPN
Manufacturer
NUMONYX
Series
Forté™r
Datasheet
1.M25P40-VMP6G.pdf
(61 pages)
Specifications of M25P40-VMP6TG
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
4M (512K x 8)
Speed
50MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-VFQFN, 8-VFQFPN
Memory Configuration
512K X 8
Ic Interface Type
Serial, SPI
Clock Frequency
50MHz
Supply Voltage Range
2.3V To 3.6V
Memory Case Style
VDFPN
No. Of Pins
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M25P40-VMP6TG
Manufacturer:
st
Quantity:
11 116
Part Number:
M25P40-VMP6TG
Manufacturer:
ST
Quantity:
20 000
Company:
Part Number:
M25P40-VMP6TG-X
Manufacturer:
STM
Quantity:
12 000
Part Number:
M25P40-VMP6TG-X
Manufacturer:
ST
Quantity:
20 000
Company:
Part Number:
M25P40-VMP6TG/TE
Manufacturer:
ST
Quantity:
2 000
6.7
Read Data Bytes at Higher Speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-
A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).
Then the memory contents, at that address, is shifted out on Serial Data output (Q), each bit
being shifted out, at a maximum frequency f
The instruction sequence is shown in
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ)
instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving
Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any
Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in
progress.
Figure 13. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence
1. Address bits A23 to A19 are Don’t Care.
S
C
D
Q
S
C
D
Q
and data-out sequence
7
32 33 34
0
6
1
High Impedance
Dummy Byte
5
2
Instruction
4
35
3
3
36 37 38 39 40 41 42 43 44 45 46
4
2
5
1
6
0
7
MSB
23
7
8
Figure
22 21
6
9 10
24 BIT ADDRESS
DATA OUT 1
5
C
13.
, during the falling edge of Serial Clock (C).
4
3
3
28 29 30 31
2
2
1
1
0
0
47
MSB
7
6
DATA OUT 2
5
4
3
2
1
0
MSB
AI04006
7
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