M25P80-VMP6TG NUMONYX, M25P80-VMP6TG Datasheet - Page 19

• Manufacturer Part Number: M25P80-VMP6TG
• Description: IC FLASH 8MBIT 75MHZ 8VFQFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P80-VMP6TG

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VFQFN, 8-VFQFPN
• Package: 8VFQFPN
• Cell Type: NOR
• Density: 8 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 64KByte x 16
• Timing Type: Synchronous
• Interface Type: Serial-SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M25P80-VMP6TG; M25P80-VMP6TGTR

6.1
6.2
Table 4.
1. The RDID instruction is available only for parts made with 110 nm Technology identified with Process letter
Write Enable (WREN)
The Write Enable (WREN) instruction
The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector
Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
Figure 7.
Write Disable (WRDI)
The Write Disable (WRDI) instruction
The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under the following conditions:
Instruction
'4'. (Details of how to find the Technology Process in the part marking are given in AN1995, see also
Section 12: Ordering Information, Standard
RES
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
Instruction set
Write Enable (WREN) instruction sequence
Release from Deep Power-
down, and Read Electronic
Signature
Release from Deep Power-
down
S
C
D
Q
Description
High Impedance
0
(Figure
(Figure
Parts.)
1
2
Instruction
instruction code
1010 1011
3
8) resets the Write Enable Latch (WEL) bit.
7) sets the Write Enable Latch (WEL) bit.
One-byte
4
5
6
ABh
7
Address
bytes
AI02281E
0
0
Dummy
bytes
3
0
1 to ∞
bytes
Data
0
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