M25P80-VMW6G NUMONYX, M25P80-VMW6G Datasheet - Page 8

• Manufacturer Part Number: M25P80-VMW6G
• Description: IC FLASH 8MBIT 75MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P80-VMW6G

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Ic Interface Type: Serial, SPI
• Clock Frequency: 75MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC W
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 15mA
• Mounting: Surface Mount
• Pin Count: 8
• Memory Configuration: 1M X 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

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Signal description
Serial Data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C).
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
Chip Select (S)
When this input signal is High, the device is deselected and Serial Data Output (Q) is at high
impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress,
the device will be in the Standby mode (this is not the Deep Power-down mode). Driving
Chip Select (S) Low enables the device, placing it in the active power mode.
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against program or erase instructions (as specified by the values in the BP2, BP1
and BP0 bits of the Status Register).