M24256-BHRDW6TP STMicroelectronics, M24256-BHRDW6TP Datasheet - Page 12
![IC EEPROM 256KBIT 1MHZ 8TSSOP](/photos/5/43/54342/497-8-tssop_sml.jpg)
M24256-BHRDW6TP
Manufacturer Part Number
M24256-BHRDW6TP
Description
IC EEPROM 256KBIT 1MHZ 8TSSOP
Manufacturer
STMicroelectronics
Datasheet
1.M24256-BWMN6TP.pdf
(42 pages)
Specifications of M24256-BHRDW6TP
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
256K (32K x 8)
Speed
1MHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Device operation
3
3.1
3.2
3.3
3.4
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Device operation
The device supports the I
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always slave in all
communications.
Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the High state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven High. A Stop condition terminates communication between the device and the
bus master. A Read instruction that is followed by NoAck can be followed by a Stop
condition to force the device into the Standby mode. A Stop condition at the end of a Write
instruction triggers the internal Write cycle.
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9
acknowledge the receipt of the eight data bits.
Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven Low.
th
clock pulse period, the receiver pulls Serial Data (SDA) Low to
2
C protocol. This is summarized in
Doc ID 6757 Rev 23
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Figure
7. Any device that sends