M24512-WMW6TG STMicroelectronics, M24512-WMW6TG Datasheet
M24512-WMW6TG
Specifications of M24512-WMW6TG
M24512-WMW6TG
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M24512-WMW6TG Summary of contents
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Features ■ 256 Kbit EEPROM addressed through the I bus 2 ■ Supports the I C bus modes: – 1 MHz Fast-mode Plus – 400 kHz Fast mode – 100 kHz Standard mode ■ Supply voltage ranges: – 1.7 V ...
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... Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5 Addressing the memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.7 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8 Page Write (memory array 3.9 Identification Page Write (M24256-DR only 3.10 Lock Identification Page (M24256-DR only 3.11 ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . . . 17 3.12 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 19 3 ...
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M24256-BF, M24256-BR, M24256-BW, M24256-DR 3.18 Read Identification Page status (locked/unlocked 3.19 Acknowledge in Read mode . . . . . . ...
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... List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Device select code (for memory array Table 3. Device select code to access the Identification page (M24256-DR only Table 4. Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 5. Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 6. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 8 ...
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M24256-BF, M24256-BR, M24256-BW, M24256-DR List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... The Start condition is followed by a device select code and Read/Write bit (RW) (as described in When writing data to the memory, the device inserts an acknowledge bit during the 9 time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way ...
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M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 2. Package connections 1. See Package mechanical data Figure 3. WLCSP connections (top view, marking side, with balls on the underside SCL V ...
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... Device select code 2.4 Write Control (WC) This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC) is driven High. When unconnected, the signal is internally read as V Write operations are allowed ...
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... SS 2.6 Supply voltage (V 2.6.1 Operating supply voltage V Prior to selecting the memory and issuing instructions to it, a valid and stable V within the specified [V Table 10). In order to secure a stable DC supply voltage recommended to decouple the V line with a suitable capacitor (usually of the order 100 nF) close to the ...
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Signal description 2 Figure Fast mode (f bus parasitic capacitance (C 100 10 Here R bus × C bus = 120 ns 4 kΩ Figure Fast mode Plus (f bus parasitic ...
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... E0, E1 and E2 are compared against the respective external pins on the memory device. Table 3. Device select code to access the Identification page (M24256-DR only) Device select code 1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared against the respective external pins on the memory device. SDA SDA Start Input ...
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Signal description Table 4. Most significant address byte b15 b14 Table 5. Least significant address byte b7 b6 12/42 M24256-BF, M24256-BR, M24256-BW, M24256-DR b13 b12 b11 Doc ID 6757 Rev 21 b10 ...
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M24256-BF, M24256-BR, M24256-BW, M24256-DR 3 Device operation The device supports the I data on to the bus is defined transmitter, and any device that reads the data receiver. The device that controls the data ...
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... Serial Data (SDA), most significant bit first). The device select code consists of a 4-bit device type identifier, and a 3-bit Chip Enable “Address” (E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is 1010b eight memory devices can be connected on a single I unique 3-bit code on the Chip Enable (E0, E1, E2) inputs ...
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M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 8. Write mode sequences with (data write inhibited) WC Byte Write WC Page Write WC (cont'd) Page Write (cont'd) ACK ACK Dev sel Byte addr Byte addr R/W ACK ACK Dev sel ...
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... If more bytes are sent than will fit up to the end of the row, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way ...
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... Write instruction are not acknowledged (NoAck). 3.10 Lock Identification Page (M24256-DR only) The Lock Identification Page instruction (Lock ID) permanently locks the Identification page in read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with the following specific conditions: ● Device Type Identifier = 1011b ● ...
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Device operation Figure 9. Write mode sequences with (data write enabled) WC Byte Write WC Page Write WC (cont'd) Page Write (cont'd) 18/42 M24256-BF, M24256-BR, M24256-BW, M24256-DR ACK ACK Dev sel Byte addr Byte addr R/W ACK ...
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... Minimizing system delays by polling on ACK During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (t shown in Table 16, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master ...
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... Sequential Random Read 3.14 Random Address Read (in memory array) A dummy Write is first performed to load the address into this address counter (as shown in Figure 11) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the contents of the addressed byte ...
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... The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter ‘rolls-over’, and the device continues to output data from memory address 00h. 3.17 ...
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Device operation 3.18 Read Identification Page status (locked/unlocked) The locked/unlocked status of the Identification page can be checked by issuing a specific truncated instruction consisting of the Identification Page Write instruction followed by one data byte. The data byte will ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR 4 Initial delivery state The device is delivered with all bits in the memory array set to 1 (each byte contains FFh). 5 Maximum rating Stressing the device outside the ratings listed in the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied ...
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DC and AC parameters 6 DC and AC parameters This section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from ...
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... Input capacitance (other pins) IN Input impedance ( (E2, E1, E0, WC) Input impedance ( (E2, E1, E0, WC) 1. Sampled only, not 100% tested. 2. E2,E1,E0: Input impedance when the memory is selected (after a Start condition). Table 13. DC characteristics (voltage range W) Symbol Parameter Input leakage current I (SCL, SDA, E0, E1, LI E2) Output leakage I LO ...
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DC and AC parameters Table 14. DC characteristics (voltage range R) Symbol Parameter Input leakage current I LI (E1, E2, SCL, SDA) I Output leakage current LO I Supply current (Read Supply current (Write) CC0 I Standby supply ...
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M24256-BF, M24256-BR, M24256-BW, M24256-DR Table 15. DC characteristics (voltage range F) Symbol Parameter Input leakage current I LI (E1, E2, SCL, SDA) I Output leakage current LO I Supply current (Read Supply current (Write) CC0 I Standby supply ...
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DC and AC parameters Table 16. 400 kHz AC characteristics Test conditions specified in Symbol Alt SCL t t CHCL HIGH t t CLCH LOW ( QL1QL2 XH1XH2 XL1XL2 ...
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M24256-BF, M24256-BR, M24256-BW, M24256-DR Table 17. 1 MHz AC characteristics Symbol Alt SCL t t CHCL HIGH t t CLCH LOW t t XH1XH2 XL1XL2 F ( QL1QL2 DXCX ...
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DC and AC parameters Figure 13. AC waveforms tXL1XL2 tXH1XH2 SCL tDLCL SDA In tCHDL tXH1XH2 Start condition SCL SDA In tCHDH Stop condition SCL tCLQV SDA Out 30/42 M24256-BF, M24256-BR, M24256-BW, M24256-DR tCHCL tCLCH tCLDX tDXCH SDA Change SDA ...
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M24256-BF, M24256-BR, M24256-BW, M24256-DR 7 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are ...
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Package mechanical data Figure 15. SO8N – 8-lead plastic small outline, 150 mils body width, package outline A2 1. Drawing is not to scale. Table 19. SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data Symbol ...
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M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 16. TSSOP8 – 8-lead thin shrink small outline, package outline Drawing is not to scale. Table 20. TSSOP8 – 8-lead thin shrink small outline, package mechanical data Symbol ...
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Package mechanical data Figure 17. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead mm, outline 1. Drawing is not to scale. 2. The central pad (the area the above ...
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M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 18. WLCSP, 0.5 mm pitch, package outline Drawing is not to scale. Table 22. WLCSP 0.5 mm pitch, package mechanical data Symbol A 0.60 A1 0.245 A2 0.355 B D 1.97 ...
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Part numbering 8 Part numbering Table 23. Ordering information scheme Example: Device type 2 M24 = I C serial access EEPROM Device function 256– = 256 Kbit (32 Kb × 8) Device family B: Without Identification page D: With additional ...
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M24256-BF, M24256-BR, M24256-BW, M24256-DR Table 24. Available M24256-BR, M24256-BW, M24256-BF products (package, voltage range, temperature grade) Package SO8N (MN) SO8W (MW) TSSOP (DW) WLCSP (CS) UFDFPN8 (MB) Table 25. Available M24256-DR products (package, voltage range, temperature grade) SO8N (MN) TSSOP ...
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... Document promoted to Full Datasheet Table of contents, and Pb-free options added. Minor wording changes in 2.0 Summary Description, Power-On Reset, Memory Addressing, Write Operations, Read Operations. V LGA8 package is Not for New Design. 5V and -S supply ranges, and Device Grade 5 removed. Absolute Maximum Ratings for V 3 ...
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... Note 1 removed from Table 13: DC characteristics (voltage range SO8W package specifications modified in data. Table 24: Available M24256-BR, M24256-BW, M24256-BF products (package, voltage range, temperature grade) M24512-x products (package, voltage range, temperature grade) Section 2.5: VSS ground added. Small text changes. V max changed and Note 1 ...
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... CLQX CLQV t and t updated in CLQX CLQV Section 8: Part numbering Reference to the SURE program removed in Previous 1 MHz M24512-HR and M24512-BHR devices replaced by new M24512-R and M24256-BR (process letter K). Doc ID 6757 Rev 21 Changes modified. modified, Figure 6: I2C Fast mode Plus ( Table 16. I test conditions modified in ...
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M24256-BF, M24256-BR, M24256-BW, M24256-DR Table 26. Document revision history (continued) Date Revision 16-Jun-2009 20-Aug-2009 13-Oct-2009 05-Nov-2009 10-Dec-2009 19-Jan-2010 04-Mar-2010 15 Part numbers updated in cover page header. I added to Table 8: Operating conditions (voltage range OL 16 Note 1and ...
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