IDT71024S12TYG IDT, Integrated Device Technology Inc, IDT71024S12TYG Datasheet - Page 6

• Manufacturer Part Number: IDT71024S12TYG
• Description: IC SRAM 1MBIT 12NS 32SOJ
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: -r

Specifications of IDT71024S12TYG

• Format - Memory: RAM
• Memory Type: SRAM
• Memory Size: 1M (128K x 8)
• Speed: 12ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-SOJ
• Density: 1Mb
• Access Time (max): 12ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 17b
• Package Type: SOJ
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 160mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Word Size: 8b
• Number Of Words: 128K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 71024S12TYG

Timing Waveform of Write Cycle No. 2
(CS
NOTES:
1. A write occurs during the overlap of a LOW CS
2. t
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS
5. Transition is measured ±200mV from steady state.
6. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, t
Timing Waveform of Write Cycle No. 1
(WE Controlled Timing)
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit)
both be active during the t
on the bus for the required t
WR
is measured from the earlier of either CS
1
1
AND CS
LOW transition or the CS
CW
DW
2
write period.
. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified t
Controlled Timing)
2
HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS
1
or WE going HIGH or CS
1
, HIGH CS
(1,4,6)
2
, and a LOW WE.
2
going LOW to the end of the write cycle.
WP
(1,4)
must be greater than or equal to t
6.42
6
Commercial and Industrial Temperature Ranges
WHZ
+ t
DW
to allow the I/O drivers to turn off and data to be placed
WP
1
.
and CS
2
must