IDT7130SA100J IDT, Integrated Device Technology Inc, IDT7130SA100J Datasheet - Page 8
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IDT7130SA100J
Manufacturer Part Number
IDT7130SA100J
Description
IC SRAM 8KBIT 100NS 52PLCC
Manufacturer
IDT, Integrated Device Technology Inc
Series
-r
Specifications of IDT7130SA100J
Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
8K (1K x 8)
Speed
100ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
52-PLCC
Density
8Kb
Access Time (max)
100ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
20b
Package Type
PLCC
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
155mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
52
Word Size
8b
Number Of Words
1K
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
Other names
7130SA100J
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT7130SA100J
Manufacturer:
IDT
Quantity:
9 520
Company:
Part Number:
IDT7130SA100J
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT7130SA100J8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
TIMING WAVEFORM OF WRITE CYCLE NO. 1, (R/
NOTES:
1. R/
2. A write occurs during the overlap (t
3. t
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the
6. Timing depends on which enable signal (
7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state
8. If
TIMING WAVEFORM OF WRITE CYCLE NO. 2, (
ADDRESS
ADDRESS
DATA
with the Output Test Load (Figure 2).
and data to be placed on the bus for the required t
the write pulse can be as short as the specified t
WR
DATA
DATA
OE
W
is measured from the earlier of
or
CE
R/
R/
is low during a R/
OUT
OE
CE
CE
CE
W
IN
W
IN
Low transition occurs simultaneously with or after the R/
must be High during all address transitions.
W
controlled write cycle, the write pulse width must be the larger of t
t
AS
t
(6)
AS
EW
CE
(6)
or t
(4)
or R/
CE
WP
) of
W
or R/
going High to the end of the write cycle.
WP
CE
W
DW
.
) is asserted last.
t
=
WZ
. If
V
IL
(7)
OE
t
and R/
AW
is High during a R/
t
AW
W
t
W
WC
=
t
Low transition, the outputs remain in the High-impedance state.
t
WP (2)
V
WC
IL.
6.01
t
CE
CE
CE
CE
CE
EW
W
W
W
W
W
(2)
CONTROLLED TIMING)
W
CONTROLLED TIMING)
t
DW
controlled write cycle, this requirement does not apply and
t
DW
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WP
or (t
WZ
t
+ t
WR
DW
(3)
t
) to allow the I/O drivers to turn off
WR
t
DH
(3)
t
OW
(1,5)
t
(1,5,8)
DH
t
HZ
t
(7)
HZ
(4)
(7)
2689 drw 10
2689 drw 11
8