CY14B256LA-SZ45XI Cypress Semiconductor Corp, CY14B256LA-SZ45XI Datasheet - Page 5

• Manufacturer Part Number: CY14B256LA-SZ45XI
• Description: IC NVSRAM 256KBIT 45NS 32SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY14B256LA-SZ45XI

• Memory Size: 256K (32K x 8)
• Package / Case: *
• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Organization: 32 K x 8
• Access Time: 45 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Current: 52 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Details of Improvement
Hardware STORE Related Improvements
STORE Initiation)
The HSB pin of the nvSRAM is an open drain I/O pin used
to indicate or initiate a STORE operation. When a STORE
operation is in progress, nvSRAM pulls the HSB pin low to
indicate that the device is busy and cannot be accessed for
read/write operation. During normal operation, the HSB pin
can be pulled low to initiate a Hardware STORE operation.
As shown in
the HSB
STK14C88-3 to CY14B256LA. All of these changes are
improvements from the original part specification and should
be considered as added benefits in your system while
converting to the new part number.
Write Latch: When a write operation is done, a ‘write latch’ is
set internally. When HSB is pulled low, nvSRAM checks
this write latch before initiating a STORE. This is done to
prevent any unnecessary loss of endurance cycles.
t
If a write latch is set and the HSB pin is pulled low,
STK14C88-3 enables 1 us time for write operations to
complete before STORE operation begins and reads and
October 5, 2009
HSB pin (Hardware STORE Busy Indication/Hardware
DELAY
Write Latch Set
pin input and output have changed from
Table
5, several timing parameters related to
Figure 2. CY14B256LA: AC Parameters Related to HSB
Figure 1. STK14C88-3: AC Parameters Related to HSB
Document No. 001-55662 Rev. **
writes are inhibited. This potentially enables inadvertent data
to be written to the nvSRAM during the t
In CY14B256LA, the t
write cycle time for any ongoing write to complete after HSB
pin is pulled low. This improvement provides better security
from inadvertent write operations.
Also, if HSB pin is pulled low externally for a minimum of
t
pulls the pin low only indicating a STORE operation within
25 ns (t
is not specified in the STK14C88-3. (See
Figure
If no writes are performed since the last STORE/RECALL
operation, STORE operation does not start when HSB is
pulled low. However, the HSB pin is still internally pulled
low for 1 us (t
CY14B256LA device does not pull the HSB pin low
internally if write latch is not set.
HSB LOW when write latch not set:
PHSB
time on CY14B256LA, the output driver of HSB pin
2)
DELAY
). This parameter for HSB low to STORE busy
DELAY
) time in the STK14C88-3 device.
DELAY
Write Latch Not Set
parameter enables only one
DELAY
duration.
Figure 1
AN55662
and
5
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