M48Z18-100PC1 STMicroelectronics, M48Z18-100PC1 Datasheet - Page 7

• Manufacturer Part Number: M48Z18-100PC1
• Description: IC NVSRAM 64KBIT 100NS 28DIP
• Manufacturer: STMicroelectronics

Specifications of M48Z18-100PC1

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 64K (8K x 8)
• Speed: 100ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP Module (600 mil), 28-EDIP
• Data Bus Width: 8 bit
• Organization: 8 Kb x 8
• Interface Type: Parallel
• Access Time: 100 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Operating Current: 80 mA
• Maximum Operating Temperature: 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Capacitance, Input: 10 pF
• Capacitance, Output: 10 pF
• Current, Input, Leakage: ±1 μA
• Current, Operating: 80 mA
• Current, Output, Leakage: ±1
• Data Retention: 11 yrs.
• Density: 64K
• Package Type: PCDIP28
• Power Dissipation: 1 W
• Temperature, Operating: 0 to +70 °C
• Time, Access: 100 ns
• Time, Fall: ≤5 ns
• Time, Rise: ≤5 ns
• Voltage, Input, High: 4.8 to 5.8 V
• Voltage, Input, Low: 0.8 V
• Voltage, Output, High: 2.4 V
• Voltage, Output, Low: 0.4 V
• Voltage, Supply: 4.5 to 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2877-5

M48Z08, M48Z18
2
Note:
2.1
Operation modes
The M48Z08/18 also has its own power-fail detect circuit. The control circuitry constantly
monitors the single 5 V supply for an out of tolerance condition. When V
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V
approximately 3 V, the control circuitry connects the battery which maintains data until valid
power returns.
Table 2.
1. See
X = V
READ mode
The M48Z08/18 is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The device architecture allows ripple-through access of data from eight of
65,536 locations in the static storage array. Thus, the unique address specified by the 13
address inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data
will be available at the data I/O pins within address access time (t
address input signal is stable, providing that the E and G access times are also satisfied. If
the E and G access times are not met, valid data will be available after the latter of the chip
enable access time (t
The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are
activated before t
the address inputs are changed while E and G remain active, output data will remain valid
for output data hold time (t
Deselect
Deselect
Deselect
WRITE
READ
READ
Mode
IH
Table 10 on page 15
or V
IL
V
Operating modes
SO
; V
4.75 to 5.5 V
4.5 to 5.5 V
SO
to V
AVQV
≤ V
V
= Battery backup switchover voltage.
PFD
or
SO
CC
ELQV
, the data lines will be driven to an indeterminate state until t
(1)
(min)
for details.
) or output enable access time (t
AXQX
(1)
Doc ID 2424 Rev 7
) but will go indeterminate until the next address access.
V
V
V
V
E
X
X
IH
IL
IL
IL
V
V
G
X
X
X
X
IH
IL
V
V
V
W
X
X
X
IH
IH
IL
GLQV
DQ0-DQ7
CC
High Z
High Z
High Z
High Z
D
D
. As V
OUT
).
IN
AVQV
CC
) after the last
Battery backup mode
CC
falls below
Operation modes
CMOS standby
is out of
Standby
Power
Active
Active
Active
AVQV
. If
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