IDT70V05L35J IDT, Integrated Device Technology Inc, IDT70V05L35J Datasheet

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IDT70V05L35J

Manufacturer Part Number
IDT70V05L35J
Description
IC SRAM 64KBIT 35NS 68PLCC
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT70V05L35J

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
64K (8K x 8)
Speed
35ns
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
70V05L35J

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT70V05L35J
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT70V05L35J8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Features
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Functional Block Diagram
©2008 Integrated Device Technology, Inc.
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
I/O
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20ns (max.)
Low-power operation
– IDT70V05S
– IDT70V05L
IDT70V05 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
0L
BUSY
- I/O
SEM
Active: 400mW (typ.)
Standby: 3.3mW (typ.)
Active: 380mW (typ.)
Standby: 660 µ W (typ.)
R/W
INT
A
OE
CE
A
12L
7L
0L
L
L
L
L
L
L
(1,2)
(2)
Decoder
Address
R/W
OE
CE
L
L
L
13
Control
I/O
HIGH-SPEED 3.3V
8K x 8 DUAL-PORT
STATIC RAM
ARBITRATION
SEMAPHORE
INTERRUPT
MEMORY
ARRAY
LOGIC
M/S
1
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one device
M/S = V
M/S = V
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 3.3V (±0.3V) power supply
Available in 68-pin PGA and PLCC, and a 64-pin TQFP
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Control
I/O
IL
IH
for BUSY input on Slave
for BUSY output flag on Master
13
Decoder
Address
R/W
CE
OE
R
R
R
OCTOBER 2008
IDT70V05S/L
2942 drw 01
OE
CE
R/W
I/O
BUSY
A
A
SEM
INT
12R
0R
0R
R
R
R
R
(2)
R
-I/O
R
DSC 2941/9
(1,2)
7R
,

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IDT70V05L35J Summary of contents

Page 1

... Features ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location ◆ ◆ ◆ ◆ ◆ High-speed access – Commercial: 15/20/25/35/55ns (max.) – Industrial: 20ns (max.) ◆ ◆ ◆ ◆ ◆ Low-power operation – IDT70V05S Active: 400mW (typ ...

Page 2

... PN64 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate oriention of the actual part-marking reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. ...

Page 3

IDT70V05S/L High-Speed 3. Dual-Port Static RAM Pin Configurations (1,2,3) 12/03/ 11L A 10L 59 58 ...

Page 4

IDT70V05S/L High-Speed 3. Dual-Port Static RAM Truth Table I: Non-Contention Read/Write Control ) ...

Page 5

IDT70V05S/L High-Speed 3. Dual-Port Static RAM Absolute Maximum Ratings ...

Page 6

IDT70V05S/L High-Speed 3. Dual-Port Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range ...

Page 7

IDT70V05S/L High-Speed 3. Dual-Port Static RAM AC Test Conditions ...

Page 8

IDT70V05S/L High-Speed 3. Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range ...

Page 9

IDT70V05S/L High-Speed 3. Dual-Port Static RAM Waveform of Read Cycles ADDR CE OE R/W DATA OUT BUSY OUT NOTES: 1. Timing depends on which signal is asserted last CE. 2. Timing depends on which signal ...

Page 10

IDT70V05S/L High-Speed 3. Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage ...

Page 11

... AS R/W DATA IN NOTES must be HIGH during all address transitions LOW CE and a LOW R/W for memory array writing cycle write occurs during the overlap ( measured from the earlier R/W (or SEM or R/W) going HIGH to the end of write cycle During this period, the I/O pins are in the output state and input signals must not be applied. ...

Page 12

IDT70V05S/L High-Speed 3. Dual-Port Static RAM Timing Waveform of Semaphore Read after Write Timing, Either Side VALID ADDRESS t AW SEM DATA R/W OE Write Cycle NOTE ...

Page 13

IDT70V05S/L High-Speed 3. Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range ...

Page 14

IDT70V05S/L High-Speed 3. Dual-Port Static RAM Timing Waveform of Write with Port-to-Port Read with BUSY ADDR "A" R/W "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ensure that ...

Page 15

IDT70V05S/L High-Speed 3. Dual-Port Static RAM Timing Waveform of Write with BUSY R/W "A" BUSY "B" R/W "B" NOTES: must be met for both BUSY input (slave) and output (master BUSY is asserted ...

Page 16

IDT70V05S/L High-Speed 3. Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range ...

Page 17

IDT70V05S/L High-Speed 3. Dual-Port Static RAM Waveform of Interrupt Timing ADDR "A" "A" R/W "A" INT "B" ADDR "B" "B" OE "B" INT "B" NOTES: 1. All timing is the same ...

Page 18

IDT70V05S/L High-Speed 3. Dual-Port Static RAM Truth Table III — Interrupt Flag R ...

Page 19

... R message (8 bits) at 1FFE or 1FFF is user-defined. If the interrupt function is not used, address locations 1FFE and 1FFF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table III for the interrupt operation. Busy Logic Busy Logic provides a hardware indication that both ports of the SRAM have accessed the same location at the same time ...

Page 20

... The eight semaphore flags reside within the IDT70V05 in a separate memory space from the Dual-Port SRAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard Static RAM ...

Page 21

... I/O device cannot tolerate any wait states. With the use of semaphores, once the two devices has determined which memory area was “off-limits” to the CPU, both the CPU and the I/O devices could access their assigned portions of memory continu- ously without any wait states ...

Page 22

IDT70V05S/L High-Speed 3. Dual-Port Static RAM Ordering Information XXXXX A 999 A Device Power Speed Package Type NOTE: 1. Contact your local sales office for Industrial temp range in other speeds, packages and powers. 2. Green parts ...

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