M48Z128Y-70PM1 STMicroelectronics, M48Z128Y-70PM1 Datasheet - Page 11

• Manufacturer Part Number: M48Z128Y-70PM1
• Description: IC NVSRAM 1MBIT 70NS 32DIP
• Manufacturer: STMicroelectronics
• Type: NVSRAMr

Specifications of M48Z128Y-70PM1

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 1M (128K x 8)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-DIP (600 mil) Module
• Data Bus Width: 8 bit
• Organization: 128 Kb x 8
• Interface Type: Parallel
• Access Time: 70 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Operating Current: 105 mA
• Maximum Operating Temperature: 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Word Size: 8b
• Density: 1Mb
• Access Time (max): 70ns
• Operating Supply Voltage (typ): 5V
• Package Type: PMDIP
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: 0C to 70C
• Pin Count: 32
• Mounting: Through Hole
• Supply Current: 105mA
• Memory Configuration: 128K X 8
• Nvram Features: Internal Battery
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: PMDIP
• No. Of Pins: 32
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2874-5

Data Retention Mode
With valid V
ates as a conventional BYTEWIDE
Should the supply voltage decay, the RAM will au-
tomatically power-fail deselect, write protecting it-
self t
become high impedance, and all inputs are treated
as “Don't care.”
If power fail detection occurs during a valid ac-
cess, the memory cycle continues to completion. If
the memory cycle fails to terminate within the time
t
below V
the internal energy source which preserves data.
The internal coin cell will maintain data in the
M48Z128/Y/V after the initial application of V
an accumulated period of at least 10 years when
V
and V
nected, and the power supply is switched to exter-
nal V
V
tion. After t
For more information on Battery Storage Life refer
to the Application Note AN1012.
V
I
switching, can produce voltage fluctuations, re-
sulting in spikes on the V
can be reduced if capacitors are used to store en-
ergy which stabilizes the V
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic by-
pass capacitor value of 0.1µF (see
recommended in order to provide the needed fil-
tering.
WP
CC
CC
CC
CC
, write protection takes place. When V
transients, including those produced by output
reaches V
Noise And Negative Going Transients
is less than V
WP
CC
CC
. Write protection continues for t
SO
after V
rises above V
ER
, the control circuit switches power to
CC
, normal RAM operation can resume.
PFD
CC
applied, the M48Z128/Y/V oper-
to allow for processor stabiliza-
SO
falls below V
. As system power returns
SO
CC
, the battery is discon-
bus. These transients
CC
bus. The energy
PFD
™
Figure
. All outputs
static RAM.
CC
ER
10.) is
CC
drops
after
for
In addition to transients that are caused by normal
SRAM operation, power cycling can generate neg-
ative voltage spikes on V
below V
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, ST recommends connecting
a schottky diode from V
nected to V
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface-mount).
Figure 10. Supply Voltage Protection
SS
V CC
M48Z128, M48Z128Y, M48Z128V*
by as much as one volt. These negative
0.1 F
CC
, anode to V
CC
CC
to V
that drive it to values
SS
). (Schottky diode
V CC
V SS
SS
DEVICE
(cathode con-
AI02169
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