IDT70261L20PF IDT, Integrated Device Technology Inc, IDT70261L20PF Datasheet
IDT70261L20PF
Specifications of IDT70261L20PF
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IDT70261L20PF Summary of contents
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... Features True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 15/20/25/35/55ns (max.) – Industrial 20/25ns (max.) Low-power operation – IDT70261S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT70261L Active: 750mW (typ.) Standby: 1mW (typ.) ...
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... This text does not indicate orientation of the actual part-marking. address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. ...
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IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Maximum Operating Temperature and Supply Voltage (1,2) Ambient Grade Temperature Commercial + Industrial - + NOTES: 1. This is ...
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IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Absolute Maximum Ratings Symbol Rating (2) V Terminal Voltage TERM with Respect to GND T Temperature BIAS Under Bias T Storage STG Temperature I DC Output OUT Current NOTES: 1. ...
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IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter Dynamic Operating Current CC SEM = V (Both Ports Active ...
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IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol READ CYCLE t Read Cycle Time RC t Address Access Time AA (3) t Chip Enable Access Time ...
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IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Waveform of Read Cycles ADDR CE OE UB, LB R/W DATA OUT BUSY OUT NOTES: 1. Timing depends on which signal is asserted last, OE, CE, LB, or UB. 2. ...
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IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Symbol Parameter WRITE CYCLE t Write Cycle Time WC (3) t Chip Enable to End-of-Write EW t Address Valid to ...
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... ( and a R for memory array writing cycle the end of write cycle. IH transition, the outputs remain in the High-impedance state. IL during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the IH and SEM = 6.42 Industrial and Commercial Temperature Ranges ...
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IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Timing Waveform of Semaphore Read after Write Timing, Either Side VALID ADDRESS SEM I R/W OE NOTES ...
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IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol BUSY TIMING (M/S BUSY Access Time from Address Match t BAA BUSY Disable Time from Address ...
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IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Timing Waveform of Write with Port-to-Port Read and BUSY (M ADDR "A" R/W "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES: ...
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IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Waveform of BUSY Arbitration Controlled by CE Timing (M ADDR "A" and "B" CE "A" (2) t APS CE "B" BUSY "B" Waveform of BUSY Arbitration Cycle Controlled ...
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IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Waveform of Interrupt Timing ADDR "A" ( "A" R/W "A" INT "B" ADDR "B" ( "B" OE "B" INT "B" NOTES: 1. All timing ...
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... The message (16 bits) at 3FFE or 3FFF is user-defined since addressable SRAM location. If the interrupt function is not used, address locations 3FFE and 3FFF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table III for the interrupt operation ...
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IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two ...
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... Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 8K of Dual-Port RAM, the processor on the left port could write and then read a zero in to Semaphore 0 ...
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... Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during Industrial and Commercial Temperature Ranges a transfer and the I/O device cannot tolerate any wait states. With the use of semaphores, once the two devices has determined which memory area was “ ...
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IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Ordering Information XXXXX A 999 Device Power Speed Package Type NOTE: 1. Contact your local sales office for Industrial temp range for other speeds, packages and powers. Datasheet Document History ...