IDT70V3579S5BCI8 IDT, Integrated Device Technology Inc, IDT70V3579S5BCI8 Datasheet - Page 12

• Manufacturer Part Number: IDT70V3579S5BCI8
• Description: IC SRAM 1.125MBIT 5NS 256BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT70V3579S5BCI8

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 1.125M (32K x 36)
• Speed: 5ns
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 70V3579S5BCI8

Timing Waveform of Left Port Write to Pipelined Right Port Read
NOTES:
1. CE
2. OE = V
3. If t
Timing Waveform of Pipelined Read-to-Write-to-Read
(OE = V
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE
3. Addresses do not have to be accessed sequentially since ADS = V
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM
are for reference use only.
be t
port will be t
ADDRESS
ADDRESS
DATA
0
CO
0
, BE
, BE
CO
DATA
< minimum specified, then data from right port read is not valid until following right port clock cycle (ie, time from write to valid read on opposite port will
ADDRESS
CLK
n
R/W
IL
+ 2 t
CLK
R/W
DATA
OUTR
n
, and ADS = V
, and ADS = V
for the Right Port, which is being read from. OE = V
DATA
INL
R
R
R
L
L
L
CYC2
CO
CLK
R/
IL
CE
CE
BE
OUT
W
+ t
IN
0
1
n
)
+ t
(3)
CYC2
(2)
CD2
IL
IL
; CE
). If t
+ t
; CE
CD2
t
MATCH
t
t
t
SW
SD
VALID
t
t
t
SA
1
SB
SC
SW
SA
1
CO
, CNTEN, and CNTRST = V
, CNTEN, and CNTRST = V
).
An
t
MATCH
t
SW
SA
> minimum, then data from right port read is available on first right port clock cycle (ie, time from write to valid read on opposite
t
t
t
t
HD
t
t
HW
HA
t
HW
HC
HB
HA
t
CH2
(1)
t
t
HW
HA
t
CYC2
t
CO
READ
t
(3)
CL2
An +1
t
CD2
IH
IH
. "NOP" is "No Operation".
.
IH
for the Left Port, which is being written to.
IL
Qn
constantly loads the address on the rising edge of the CLK; numbers
t
SW
An + 2
MATCH
NO
t
HW
NOP
6.42
12
t
CKHZ
(4)
t
SD
Dn + 2
t
An + 2
CD2
t
HD
WRITE
Industrial and Commercial Temperature Ranges
An + 3
VALID
MATCH
NO
t
CKLZ
t
READ
DC
An + 4
t
CD2
Qn + 3
4830 drw 09
4830 drw 08
(1,2)