IDT70V3379S5BFI IDT, Integrated Device Technology Inc, IDT70V3379S5BFI Datasheet - Page 11

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IDT70V3379S5BFI

Manufacturer Part Number
IDT70V3379S5BFI
Description
IC SRAM 576KBIT 5NS 208FBGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT70V3379S5BFI

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Synchronous
Memory Size
576K (32K x 18)
Speed
5ns
Interface
Parallel
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
70V3379S5BFI

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT70V3379S5BFI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT70V3379S5BFI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Timing Waveform of Read Cycle for Pipelined Operation
NOTES:
1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
2. ADS = V
3. The output is disabled (High-Impedance state) by CE
4. Addresses do not have to be accessed sequentially since ADS = V
5. If UB or LB was HIGH, then the appropriate Byte of DATA
Timing Waveform of a Multi-Device Pipelined Read
NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V3379 for this waveform,
2. UB, LB, OE, and ADS = V
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM
ADDRESS
ADDRESS
Truth Table 1.
are for reference use only.
DATA
DATA
and are setup for depth expansion in this example. ADDRESS
ADDRESS
UB, LB
DATA
CE
CE
OUT(B1)
OUT(B2)
CLK
R/
IL
CE
CE
(0-3)
OUT
CLK
0(B1)
0(B2)
OE
, CNTEN and CNTRST = V
(B1)
(B2)
W
0
1
(4)
(1)
t
t
t
t
t
t
t
t
SC
SC
SA
SA
SW
SA
SC
SB
An
IL
A
A
; CE
0
0
t
t
t
t
t
HC
HC
t
t
t
HA
HA
HW
HC
HB
HA
t
CH2
(1 Latency)
1(B1)
t
CH2
t
CYC2
, CE
IH
.
1(B2)
t
CL2
t
CYC2
, R/W, CNTEN, and CNTRST = V
A
A
t
CKLZ
1
1
t
CL2
0
(1)
t
An + 1
CD2
= V
OUT
IH
, CE
for Qn + 2 would be disabled (High-Impedance state).
(B1)
t
t
1
t
SC
SC
CD2
= V
= ADDRESS
Q
A
A
IL
2
2
0
IL
constantly loads the address on the rising edge of the CLK; numbers
t
t
t
HC
HC
DC
, UB, LB = V
t
6.42
CD2
11
(B2)
IH
.
in this situation.
IH
t
An + 2
SB
(5)
Qn
following the next rising edge of the clock. Refer to
Q
A
A
3
1
3
t
t
t
HB
DC
t
CKHZ
CKLZ
t
DC
t
CD2
Industrial and Commercial Temperature Ranges
Qn + 1
A
A
Q
4
4
2
(1,2)
t
t
t
OHZ
CKHZ
CKLZ
t
An + 3
t
SC
CD2
(3)
t
HC
(2)
t
t
OE
OLZ
A
A
Q
5
5
3
t
t
CKHZ
CKLZ
Qn + 2
t
CD2
4833 drw 06
4833 drw 07
(5)
A
A
Q
6
6
4

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