SST25VF512A-33-4C-QAE Microchip Technology, SST25VF512A-33-4C-QAE Datasheet - Page 5

• Manufacturer Part Number: SST25VF512A-33-4C-QAE
• Description: IC FLASH SER 512K 33MHZ 8WSON
• Manufacturer: Microchip Technology

Specifications of SST25VF512A-33-4C-QAE

• Memory Type: FLASH
• Memory Size: 512K (64K x 8)
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-WSON
• Format - Memory: FLASH
• Speed: 33MHz
• Interface: SPI Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Architecture: Sectored
• Interface Type: 4-Wire
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 10 mA
• Mounting Style: SMD/SMT
• Organization: 4 KB x 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

512 Kbit SPI Serial Flash
SST25VF512A
Hold Operation
HOLD# pin is used to pause a serial sequence underway
with the SPI flash memory without resetting the clocking
sequence. To activate the HOLD# mode, CE# must be in
active low state. The HOLD# mode begins when the SCK
active low state coincides with the falling edge of the
HOLD# signal. The HOLD mode ends when the HOLD#
signal’s rising edge coincides with the SCK active low state.
If the falling edge of the HOLD# signal does not coincide
with the SCK active low state, then the device enters Hold
mode when the SCK next reaches the active low state.
Similarly, if the rising edge of the HOLD# signal does not
Write Protection
The SST25VF512A provides software Write protection.
The Write Protect pin (WP#) enables or disables the lock-
down function of the status register. The Block-Protection
bits (BP1, BP0, and BPL) in the status register provide
Write protection to the memory array and the status regis-
ter. See Table 5 for Block-Protection description.
Write Protect Pin (WP#)
The Write Protect (WP#) pin enables the lock-down func-
tion of the BPL bit (bit 7) in the status register. When WP#
is driven low, the execution of the Write-Status-Register
(WRSR) instruction is determined by the value of the BPL
bit (see Table 3). When WP# is high, the lock-down func-
tion of the BPL bit is disabled.
©2006 Silicon Storage Technology, Inc.
HOLD#
FIGURE 3: H
SCK
OLD
Active
C
ONDITION
W
AVEFORM
Hold
5
coincide with the SCK active low state, then the device
exits in Hold mode when the SCK next reaches the active
low state. See Figure 3 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-
impedance state while SI and SCK can be V
If CE# is driven active high during a Hold condition, it resets
the internal logic of the device. As long as HOLD# signal is
low, the memory remains in the Hold condition. To resume
communication with the device, HOLD# must be driven
active high, and CE# must be driven active low. See Figure
18 for Hold timing.
TABLE 3: C
WP#
H
L
L
Active
R
ONDITIONS TO EXECUTE
EGISTER
BPL
X
1
0
Hold
(WRSR) I
Execute WRSR Instruction
Not Allowed
Allowed
Allowed
NSTRUCTION
S71264-02-000
Active
W
RITE
IL
Data Sheet
or V
-S
1264 F03.0
TATUS
IH
T3.0 1264
.
1/06
-