CAT24C256YI-G ON Semiconductor, CAT24C256YI-G Datasheet - Page 6

• Manufacturer Part Number: CAT24C256YI-G
• Description: IC EEPROM 256KBIT 400KHZ 8TSSOP
• Manufacturer: ON Semiconductor

Specifications of CAT24C256YI-G

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 256K (32K x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TSSOP
• Organization: 32 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Current: 1 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 3.3 V, 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WRITE OPERATIONS
Byte Write
by Slave address, two byte address and data to be written
(Figure 6). The Slave acknowledges all 4 bytes, and the
Master then follows up with a STOP, which in turn starts the
internal Write operation (Figure 7). During internal Write,
the Slave will not acknowledge any Read or Write request
from the Master.
Page Write
in 512 pages of 64 bytes each. A two byte address word,
following the Slave address, points to the first byte to be
written. The most significant bit of the address word is ‘don’t
care’, the next 9 bits identify the page and the last 6 bits
identify the byte within the page. Up to 64 bytes can be
written in one Write cycle (Figure 8).
incremented after each data byte is loaded. If the Master
transmits more than 64 data bytes, then earlier bytes will be
overwritten by later bytes in a ‘wrap−around’ fashion
In Byte Write mode the Master sends a START, followed
The CAT24C256 contains 32,768 bytes of data, arranged
The internal byte address counter is automatically
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(within the selected page). The internal Write cycle starts
immediately following the STOP.
Acknowledge Polling
CAT24C256 is busy writing or is ready to accept commands.
Polling is implemented by interrogating the device with a
‘Selective Read’ command (see READ OPERATIONS).
as long as internal Write is in progress.
Hardware Write Protection
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the operation of
the CAT24C256. The state of the WP pin is strobed on the
last falling edge of SCL immediately preceding the first data
byte (Figure 9). If the WP pin is HIGH during the strobe
interval, the CAT24C256 will not acknowledge the data byte
and the Write request will be rejected.
Delivery State
Acknowledge polling can be used to determine if the
The CAT24C256 will not acknowledge the Slave address,
With the WP pin held HIGH, the entire memory is
The CAT24C256 is shipped erased, i.e., all bytes are FFh.