DS2430AP+T&R Maxim Integrated Products, DS2430AP+T&R Datasheet - Page 17

• Manufacturer Part Number: DS2430AP+T&R
• Description: IC EEPROM 256BIT 6TSOC
• Manufacturer: Maxim Integrated Products

Specifications of DS2430AP+T&R

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 256 (32 x 8)
• Interface: 1-Wire Serial
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 6-TSOC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Speed: -

Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Note 17:
Note 18:
Note 19:
Note 20:
Note 21:
Note 22:
Note 23:
Note 24:
EEPROM
Programming Current
Programming Time
Write/Erase Cycles (En-
durance) (Notes 20, 21)
Data Retention (Notes 22,
23, 24)
PARAMETER
Specifications at T
System requirement.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire
recovery times. The specified value here applies to systems with only one device and with the minimum t
more heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may
be required. If longer t
Maximum value represents the internal parasite capacitance when V
to pull up the data line, 2.5µs after V
communications.
Guaranteed by design, characterization and/or simulation only. Not production tested.
V
timing, and capacitive loading on DATA. Lower V
all lead to lower values of V
Voltage below which, during a falling edge on DATA, a logic 0 is detected.
The voltage on DATA needs to be less or equal to V
level.
Voltage above which, during a rising edge on DATA, a logic 1 is detected.
After V
detected as logic '0'.
The I-V characteristic is linear for voltages less than 1V.
Applies to a single device attached to a 1-Wire line.
The earliest recognition of a negative edge is possible at t
edge.
Defines maximum possible bit rate. Equal to 1/(t
Interval after t
present. Minimum limit is t
 in Figure 10 represents the time required for the pullup circuitry to pull the voltage on DATA up from V
V
 in Figure 10 represents the time required for the pullup circuitry to pull the voltage on DATA up from V
input high threshold of the bus master. The actual maximum duration for the master to pull the line low is
t
Current drawn from DATA during the EEPROM programming interval. The pullup circuit on DATA during the
programming interval should be such that the voltage drop been V
increases with increased V
Interval begins t
copy sequence. Interval ends once the device's self-timed EEPROM programming cycle is complete and the
current drawn by the device has returned from I
Write-cycle endurance is degraded as T
Not 100% production-tested; guaranteed by reliability monitor sampling.
Data retention is degraded as T
Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production
test to data sheet limit at operating temperature range is established by reliability testing.
EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at
elevated temperatures is not recommended; the device can lose its write capability after 10 years at +125°C or 40
years at +85°C.
RLmax
TL
TH
, V
. The actual maximum duration for the master to pull the line low is t
+ t
TH
TH
, and V
F
.
is crossed during a rising edge on DATA, the voltage on DATA has to drop by at least V
RSTL
HY
REHmax
SYMBOL
A
during which a bus master is guaranteed to sample a logic-0 on DATA if there is a DS2430A
are a function of the internal supply voltage which is itself a function of V
= -40°C are guaranteed by design only and not production-tested.
I
t
N
PROG
REC
PROG
t
after the trailing rising edge on DATA for the last timeslot of the validation key for a valid
DR
CY
is used, higher R
PUP
PDH(max)
TL
.
, V
A
(Notes 5, 18)
(Note 19)
At 25°C
At 85°C (worst case)
At 85°C (worst case)
increases.
TH
; maximum limit is t
, and V
PUP
A
has been applied the parasite capacitance will not affect normal
increases.
CONDITIONS
HY
PUP
.
values may be able to be tolerated.
17 of 19
PROG
W0L(min)
PUP
IL(MAX)
to I
, higher R
PDH(min)
L
+ t
.
REH
REC(min)
at all times the master is driving DATA to a logic-0
after V
+ t
PUP
).
PDL(min)
PUP
, shorter t
PUP
TH
and DATA is less than 0.25V. Current
has been reached on the preceding rising
is first applied. If a 2.2k resistor is used
.
W1Lmax
MIN
200k
50k
40
REC
, and heavier capacitive loading
+ t
F
and t
TYP
W0Lmax
PUP
MAX UNITS
+ t
, R
0.5
10
F
HY
PUP
respectively.
to be
, 1-Wire
DS2430A
REC
IL
IL
years
mA
ms

to
to the
. For