24LC32/P Microchip Technology, 24LC32/P Datasheet - Page 10

• Manufacturer Part Number: 24LC32/P
• Description: IC EEPROM 32KBIT 400KHZ 8DIP
• Manufacturer: Microchip Technology

Specifications of 24LC32/P

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 32K (4K x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 6.0 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification

24LC32
7.0
7.1
The A0..A2 inputs are used by the 24LC32 for multiple
device operation and conform to the two-wire bus stan-
dard. The levels applied to these pins define the
address block occupied by the device in the address
map. A particular device is selected by transmitting the
corresponding bits (A2, A1, A0) in the control byte
(Figure 3-3).
FIGURE 7-1:
FIGURE 7-2:
DS21072G-page 10
Last 2 bytes
loaded into
page 0 of cache.
1 Write command initiated at byte 0 of page 3 in the array;
3 Write from cache into array initiated by STOP bit.
First data byte is loaded into the cache byte 0.
Page 0 of cache written to page 3 of array.
Write cycle is executed after every page is written.
6
page 0
page 0
Last 3 pages in cache written to next row in array.
PIN DESCRIPTIONS
A0, A1, A2 Chip Address Inputs
page 1 page 2
page 1 page 2
page 0
page 0 page 1 page 2
CACHE WRITE TO THE ARRAY STARTING AT A PAGE BOUNDARY
CACHE WRITE TO THE ARRAY STARTING AT A NON-PAGE BOUNDARY
3
cache
byte 0
cache
byte 0
page 1 page 2
cache
byte 1
byte 1
cache
byte 0
cache page 0
1 Write command initiated; 64 bytes of data
loaded into cache starting at byte 2 of page 0.
cache
byte 2
byte 1
4 Write from cache into array initiated by STOP bit.
• • •
byte 0
5
Page 0 of cache written to page 3 of array.
Write cycle is executed after every page is written.
• • •
Last page in cache written to page 2 in next row.
byte 2
byte 7
cache
byte 1
cache
byte 7
page 3
page 3
byte 3
cache page 1
bytes 8-15
• • •
cache page 1
bytes 8-15
byte 4
7.2
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to V
400 kHz)
For normal data transfer SDA is allowed to change only
during SCL low.
reserved for indicating the START and STOP condi-
tions.
7.3
This input is used to synchronize the data transfer from
and to the device.
2 64 bytes of data are loaded into cache.
byte 7
4 Remaining pages in cache are written
• • •
cache page 2
bytes 16-23
to sequential pages in array.
cache page 2
bytes 16-23
SDA Serial Address/Data Input/Output
SCL Serial Clock
page 4
page 4
byte 7
CC
2 Last 2 bytes loaded 'roll over'
(typical 10K
to beginning.
• • •
• • •
page 4
page 4
Changes during SCL high
• • •
5
• • •
Remaining bytes in cache are
written sequentially to array.
2004 Microchip Technology Inc.
page 7
page 7
• • •
• • •
cache page 7
bytes 56-63
for 100 kHz, 2 K
array row n
array row n + 1
cache page 7
page 7
page 7
bytes 56-63
array
array
row
n + 1
row n
are
for