24LC164-I/P Microchip Technology, 24LC164-I/P Datasheet - Page 8

• Manufacturer Part Number: 24LC164-I/P
• Description: IC EEPROM 16KBIT 400KHZ 8DIP
• Manufacturer: Microchip Technology

Specifications of 24LC164-I/P

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 16K (2K x 8)
• Speed: 100kHz, 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification

24LC164
FIGURE 7-1:
FIGURE 7-2:
FIGURE 7-3:
8.0
8.1
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal. Therefore, the SDA bus requires a pul-
lup resistor to V
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL LOW. Changes during SCL HIGH are
reserved for indicating the START and STOP condi-
tions.
8.2
This input is used to synchronize the data transfer from
and to the device.
DS21093I-page 8
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
PIN DESCRIPTIONS
SDA Serial Address/Data Input/
Output
SCL Serial Clock
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
CC
(typical 10k
CONTROL
CURRENT ADDRESS READ
RANDOM READ
SEQUENTIAL READ
S
BYTE
S
T
A
R
T
1 A2 A1A0B2B1B0
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
A
C
K
CONTROL
BYTE
for 100 kHz, 2k
DATA (n)
C
A
K
S 1 A2A1A0B2B1B0
R
ADDRESS (n)
S
T
A
T
A
C
K
WORD
for
DATA (n + 1)
CONTROL
BYTE
C
A
K
8.3
This pin must be connected to either V
If tied to V
(read/write the entire memory 000-7FF).
If tied to V
entire memory will be write-protected. Read operations
are not affected.
This feature allows the user to use the 24LC164 as a
serial ROM when WP is enabled (tied to V
8.4
These pins are used to configure the proper chip
address in multiple-chip applications (more than one
24LC164 on the same bus). The levels on these pins
are compared to the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to eight 24LC164s may be connected to the same
bus. These pins must be connected to either V
V
S
A
R
S
T
T
CC
Note:
A
C
K
A
C
K
.
CONTROL
DATA (n + 2)
BYTE
WP
A0, A1, A2
DATA (n)
CC
The level on A1 is compared to the
inverse of the slave address.
SS
, WRITE operations are inhibited. The
, normal memory operation is enabled
A
C
K
A
C
K
 2004 Microchip Technology Inc.
N
O
C
A
K
O
P
S
T
P
DATA (n)
DATA (n + X)
SS
N
O
A
C
K
or V
S
T
O
P
P
CC
).
N
O
C
CC
A
K
S
T
O
P
P
.
SS
or